Computer Organization and Architecture PYQs for GATE CS

GATE CS Computer Organization and Architecture: 6 chapters, 66 previous year questions (100% of Computer Organization and Architecture), 1032 practice questions and one solved question from each chapter.

About Computer Organization and Architecture Previous Year Questions (PYQs)

66 previous year questions from Computer Organization and Architecture in GATE CS, grouped by chapter with the exam year, answer key and step-by-step solution for each.

Computer Organization and Architecture Weightage in GATE CS

Computer Organization and Architecture accounts for 66 of 66 Computer Organization and Architecture previous year questions in our bank (100%), about 6.6 per paper across 10 papers.

Computer Organization and Architecture Chapter Matrix

Chapter	Topics	PYQs	Share of unit PYQs	Practice questions
Number Representation and Computer Arithmetic	Signed Integer Representation and Arithmetic Overflow, Booth Multiplication Algorithm, IEEE 754 Encoding, Decoding and Special Values, IEEE 754 Floating-Point Arithmetic, Endianness and Byte Ordering	14	21%	198
Instruction Set, Datapath and Memory Organization	Instruction Set Architecture and Instruction Encoding, Addressing Modes and Effective Address Computation, Load-Store Architecture and Assembly Translation, Memory Block Organization and Address Decoding, Processor Datapath and Operand Selection	11	17%	192
Processor Performance, Pipelining and Hazards	Pipeline Timing, Latency and Throughput, Pipeline CPI, Clock Rate and Stall Performance, Data Dependencies, Hazards and Forwarding, Control Hazards and Branch Prediction, Parallel Speedup and Multicore Performance	13	20%	200
Cache Memory, Memory Hierarchy and Address Translation	Direct-Mapped Cache Addressing and Tag Calculation, Set-Associative Cache Organization and Associativity, Cache Access Sequences and Conflict Misses, Cache Write Policies, Allocation and Replacement, Cache Performance and Effective Memory Access Time, TLB, Virtual Memory and Cache Interaction	18	27%	274
Input-Output, Interrupts and DMA	Interrupt Processing and Priority Mechanisms, DMA Modes, Throughput and Bulk Data Transfer, Polling and I/O Processing Overhead	7	11%	121
Secondary Storage and Disk Performance	Disk Geometry, Capacity and Cylinders, Disk Access Time, Seek and Rotational Latency	3	5%	47

One Solved Question from Each Computer Organization and Architecture Chapter

Question 1 · Number Representation and Computer Arithmetic · 2026_Set2 NAT

The 32-bit IEEE 754 single precision representation of a number is 0xC2710000. The number in decimal representation is ________. <i>(rounded off to two decimal places)</i>

Correct Answer:

-60.25

Step-by-Step Solution

Key idea: Decode an IEEE 754 single-precision hexadecimal representation into its decimal equivalent by extracting the sign, exponent, and mantissa.

Step 1: Convert the hex value 0xC2710000 to binary.

C = 1100, 2 = 0010, 7 = 0111, 1 = 0001

Binary: 1100 0010 0111 0001 0000 0000 0000 0000

Step 2: Extract the fields.

Sign bit (1 bit): 1 (indicates a negative number).
Exponent field (8 bits): 10000100.
Mantissa field (23 bits): 11100010000000000000000.

Step 3: Decode the exponent.

Biased exponent = 10000100_2 = 132.

Actual exponent = 132 - 127 (bias) = 5.

Step 4: Decode the mantissa.

The implicit leading bit is 1, so the significand is 1.1110001_2.

Step 5: Calculate the decimal value.

Value = -1 × (1.1110001_2) × 2^5

Multiplying by 2^5 shifts the binary point 5 places to the right:

1.1110001_2 × 2^5 = 111100.01_2

Step 6: Convert binary to decimal.

Integer part: 111100_2 = 32 + 16 + 8 + 4 = 60.

Fractional part: .01_2 = 1/4 = 0.25.

Combined value = -60.25.

Question 2 · Instruction Set, Datapath and Memory Organization · 2026_Set2 MCQ

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

A.
8
B.
4
C.
64
D.
16

Correct Answer:

Step-by-Step Solution

Key idea: This is an expanding opcode instruction encoding question, recognisable by the mention of "variable-sized opcodes" and multiple instruction types with different operand counts.

Why this method applies: In expanding opcode techniques, unused opcode patterns from a shorter opcode field are "expanded" into longer opcode fields by sacrificing operand bits. We must track the number of available patterns at each stage.

Step 1: Analyze the base constraints.

Total instruction length = 2 bytes = 16 bits.

Number of registers = 16. Bits per register field = $lo g_{2} (16) = 4$ bits.

Step 2: Analyze M-type instructions.

Format: Opcode + 2 Register operands + 6-bit immediate.

Operand bits = $4 + 4 + 6 = 14$ bits.

Opcode bits = $16 - 14 = 2$ bits.

Total possible 2-bit patterns = $2^{2} = 4$ .

M-type uses 2 opcodes.

Remaining patterns for expansion = $4 - 2 = 2$ .

Step 3: Analyze R-type instructions.

Format: Opcode + 3 Register operands.

Operand bits = $4 + 4 + 4 = 12$ bits.

Opcode bits = $16 - 12 = 4$ bits.

Each of the 2 remaining 2-bit patterns can be expanded into $2^{2} = 4$ four-bit patterns.

Total available 4-bit patterns = $2 \times 4 = 8$ .

R-type uses 7 opcodes.

Remaining patterns for expansion = $8 - 7 = 1$ .

Step 4: Analyze C-type instructions.

Format: Opcode + 1 Register operand + 6-bit offset.

Operand bits = $4 + 6 = 10$ bits.

Opcode bits = $16 - 10 = 6$ bits.

The 1 remaining 4-bit pattern can be expanded into $2^{2} = 4$ six-bit patterns.

Total available 6-bit patterns = $1 \times 4 = 4$ .

Therefore, the maximum number of unique C-type opcodes is 4.

Answer: Option B.

Question 3 · Processor Performance, Pipelining and Hazards · 2026_Set2 NAT

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design,

30%

of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places)

Note:

1 G = 1 0^{9}

Correct Answer:

2.34

Step-by-Step Solution

Key idea: This is a pipelining speedup NAT with clock rate change, recognisable because it gives the clock frequencies and CPI/stall information for both non-pipelined and pipelined designs.

Step 1: Calculate the execution time per instruction for the non-pipelined design.

Clock frequency $f_{n p} = 1.6$ GHz.

Cycles per instruction $C P I_{n p} = 5$ .

Time per instruction $T_{n p} = \frac{C P I _{n p}}{f _{n p}} = \frac{5}{1.6}$ time units.

Step 2: Calculate the execution time per instruction for the pipelined design.

Clock frequency $f_{p} = 1.2$ GHz.

Base CPI = 1.

Stall penalty: 30% of instructions encounter a 2-cycle stall.

Average stall cycles per instruction = $0.3 \times 2 = 0.6$ .

Actual CPI $C P I_{p} = 1 + 0.6 = 1.6$ .

Time per instruction $T_{p} = \frac{C P I _{p}}{f _{p}} = \frac{1.6}{1.2}$ time units.

Step 3: Calculate the speedup.

Speedup = $\frac{T _{n p}}{T _{p}} = \frac{5/1.6}{1.6/1.2} = \frac{5}{1.6} \times \frac{1.2}{1.6} = \frac{6}{2.56} = 2.34375$ .

Rounded to two decimal places, this is 2.34.

Answer: 2.34

Question 4 · Cache Memory, Memory Hierarchy and Address Translation · 2026_Set2 MSQ

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,…

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).

P : 0 x 845 B 32, Q : 0 x 845 B 26, R : 0 x 845 B 36, S : 0 x 846 B 32

Which of the following statements is/are true?

Note:

1 K = 2^{10}

and

1 M = 2^{20}

A.
Every access to P results in a cache miss
B.
Every access to R results in a cache hit
C.
Every access to Q results in a cache miss
D.
Except the first access to S, all subsequent accesses to S result in cache hits

Correct Answer:

["A","B"]

Step-by-Step Solution

Key idea: this is a cache access sequence tracing question, recognisable because it gives specific hex addresses and a repeating access pattern, requiring you to map each address to a cache line and track hits/misses over multiple rounds.

Step 1: Determine the cache parameters. Cache size = 4 KB = $2^{12}$ bytes. Block size = 16 bytes = $2^{4}$ bytes. Number of lines = $2^{12} / 2^{4} = 2^{8} = 256$ . Index bits = 8. Offset bits = 4.

Step 2: Extract the index and tag for each address. The offset is the last 4 bits (1 hex digit). The index is the next 8 bits (2 hex digits). The tag is the remaining bits.

P (0x845B32): Offset = 2, Index = B3, Tag = 845.
Q (0x845B26): Offset = 6, Index = B2, Tag = 845.
R (0x845B36): Offset = 6, Index = B3, Tag = 845.
S (0x846B32): Offset = 2, Index = B3, Tag = 846.

Step 3: Notice that P and R have the exact same Tag and Index. They map to the same cache block. Q maps to line B2. S maps to line B3 but has a different tag (846).

Step 4: Trace the sequence P, Q, R, S for Round 1:

P: Line B3 miss. Loads block (Tag 845).
Q: Line B2 miss. Loads block (Tag 845).
R: Line B3 hit. (Block is already there from P).
S: Line B3 miss. Loads block (Tag 846), evicting P/R.

Step 5: Trace Round 2 and beyond:

P: Line B3 miss (evicts S).
Q: Line B2 hit (never evicted).
R: Line B3 hit (loaded by P in this round).
S: Line B3 miss (evicts P/R).

Step 6: Evaluate the options. P always misses (True). R always hits (True). Q misses first, then hits (False). S always misses (False).

Answer: A, B

Question 5 · Input-Output, Interrupts and DMA · 2026_Set2 MCQ

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2 ?

A.
Both S1 and S2 are true
B.
Both S1 and S2 are false
C.
S1 is true and S2 is false
D.
S1 is false and S2 is true

Correct Answer:

Step-by-Step Solution

Key idea: This is an interrupt mechanism comparison question, testing the definitions of vectored vs non-vectored interrupts and daisy-chaining.

Step 1: Analyze S1. In a non-vectored interrupt, the hardware does not provide the ISR address. The CPU must execute a software routine (like polling) to identify the interrupt source, which takes more time. In a vectored interrupt, the hardware directly provides the vector address, making it faster. Thus, S1 is True.

Step 2: Analyze S2. In a daisy-chain interrupt mechanism, the interrupt acknowledge signal is passed serially through a chain of devices. The device that requested the interrupt blocks the signal and places its vector address on the bus. The CPU does not individually poll all devices; the hardware chain resolves the priority. Thus, S2 is False.

Step 3: Conclude that S1 is true and S2 is false.

Answer: C

Question 6 · Secondary Storage and Disk Performance · 2026_Set1 NAT

Consider a hard disk with a rotational speed of 15000 rpm. The time to move the read/write head from a track to its adjacent track is 1 millisecond. Initially, the head is on track 0. The number of sectors per track is 400. The sector size is 1024 bytes. It is necessary to transfer data from 10 randomly located sectors in each of the following tracks in the order: 5, 12 and 7.

The total time for the data transfer (in milliseconds) from the hard disk is _________. (rounded off to one decimal place)

Correct Answer:

77.30

Step-by-Step Solution

Insight: Sectors are randomly located within their respective tracks, so we seek to each track once, then pay rotational latency for each of the 10 sectors.

Exam route: For each track, add seek time to $10 \times (T_{l a t} + T_{t r an s})$ . Sum the three tracks.

Learning route:

$T_{r o t} = \frac{60000}{15000} = 4$ ms.
$T_{l a t} = \frac{4}{2} = 2$ ms.
$T_{t r an s} = \frac{4}{400} = 0.01$ ms.
Track 5: Seek from 0 to 5 = 5 ms. Data = $10 \times (2 + 0.01) = 20.1$ ms. Total = 25.1 ms.
Track 12: Seek from 5 to 12 = 7 ms. Data = 20.1 ms. Total = 27.1 ms.
Track 7: Seek from 12 to 7 = 5 ms. Data = 20.1 ms. Total = 25.1 ms.
Grand total = $25.1 + 27.1 + 25.1 = 77.3$ ms.

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Computer Organization and Architecture PYQs for GATE CS

About Computer Organization and Architecture Previous Year Questions (PYQs)

Computer Organization and Architecture Weightage in GATE CS

Computer Organization and Architecture Chapter Matrix

More from Computer Organization and Architecture

One Solved Question from Each Computer Organization and Architecture Chapter

Step-by-Step Solution

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Step-by-Step Solution

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