Input-Output, Interrupts and DMA PYQs for GATE CS

Solve 7+ Input-Output, Interrupts and DMA previous year questions for GATE CS with answers and detailed solutions. Free sample questions below.

Chapter Roadmap: Input-Output, Interrupts and DMA

Chapter Roadmap

Input-Output, Interrupts and DMA

1. Interrupt Processing and Priority

Hardware signals, ISR sequence, vectored vs non-vectored, daisy chaining.

Weightage: Moderate

2. DMA Modes, Throughput and Bulk Transfer

Cycle stealing, burst mode, data transfer rate calculations.

Weightage: High

3. Polling and I/O Processing Overhead

Programmed I/O, CPU cycle consumption, overhead analysis.

Weightage: Low

Goal: Master how the CPU efficiently manages external devices without wasting cycles, transitioning from software polling to hardware-driven interrupts and DMA.

Interrupt Processing and Priority Mechanisms

Input-Output, Interrupts and DMA

Interrupt Processing and Priority Mechanisms

The foundation of how a CPU reacts to external events efficiently.

What you will learn here:

The exact sequence of steps the processor takes when an interrupt arrives.
The critical difference between vectored and non-vectored interrupts.
How daisy-chaining resolves priority conflicts in hardware.
Common traps in calculating interrupt overhead and context switching.

Input-Output, Interrupts and DMA: Solved Questions with Step-by-Step Explanations (7 Problems)

Question 1 · Computer Organization and Architecture · 2026_Set2 MCQ

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2 ?

A.
Both S1 and S2 are true
B.
Both S1 and S2 are false
C.
S1 is true and S2 is false
D.
S1 is false and S2 is true

Correct Answer:

Step-by-Step Solution

Key idea: This is an interrupt mechanism comparison question, testing the definitions of vectored vs non-vectored interrupts and daisy-chaining.

Step 1: Analyze S1. In a non-vectored interrupt, the hardware does not provide the ISR address. The CPU must execute a software routine (like polling) to identify the interrupt source, which takes more time. In a vectored interrupt, the hardware directly provides the vector address, making it faster. Thus, S1 is True.

Step 2: Analyze S2. In a daisy-chain interrupt mechanism, the interrupt acknowledge signal is passed serially through a chain of devices. The device that requested the interrupt blocks the signal and places its vector address on the bus. The CPU does not individually poll all devices; the hardware chain resolves the priority. Thus, S2 is False.

Step 3: Conclude that S1 is true and S2 is false.

Answer: C

Question 2 · Computer Organization and Architecture · 2025_Set1 MCQ

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

A.
(iii), (i), (ii)
B.
(i), (iii), (ii)
C.
(i), (ii), (iii)
D.
(iii), (ii), (i)

Correct Answer:

Step-by-Step Solution

Key idea: This is an interrupt handling sequence question, testing the exact order of hardware and software actions when an asynchronous interrupt occurs.

Step 1: The processor cannot abort an instruction mid-execution without corrupting the system state. Therefore, it must first finish the currently executing instruction. This is step (iii).

Step 2: Before jumping to the ISR, the processor must save the return address so it can resume the interrupted program later. This is done by saving the content of the Program Counter (PC). This is step (i).

Step 3: Finally, the processor loads the PC with the starting address of the ISR to begin executing the interrupt service routine. This is step (ii).

Step 4: The correct sequence is (iii), (i), (ii).

Answer: A

Question 3 · Computer Organization and Architecture · 2024_Set2 MCQ

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

A.
2,56,000
B.
3,200
C.
25,60,000
D.
32,000

Correct Answer:

Step-by-Step Solution

Key idea: This is a DMA throughput calculation question, similar to P1 but with different units and a larger transfer size per cycle.

Step 1: Calculate total CPU cycles per second. The processor is 4 MHz, which is $4 \times 1 0^{6}$ cycles/second.

Step 2: Calculate DMA cycles per second. 1% of total cycles: $0.01 \times 4 \times 1 0^{6} = 40, 000$ cycles/second.

Step 3: Relate cycles to data. Each cycle transfers 8 bytes.

Step 4: Calculate total bytes per second: $40, 000 \times 8 = 320, 000$ bytes/second.

Step 5: Convert to bits per second (since the question asks for bits per second). $320, 000 bytes/sec \times 8 bits/byte = 2, 560, 000$ bits/second.

Step 6: Match with the Indian numbering system format in the options. 2,560,000 is written as 25,60,000.

Answer: C

Question 4 · Computer Organization and Architecture · 2024_Set1 MCQ

Which one of the following statements is FALSE?

A.
In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
B.
For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
C.
Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
D.
The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Correct Answer:

Step-by-Step Solution

Key idea: This is a "find the false statement" question testing the detailed properties of various I/O and DMA modes.

Step 1: Analyze Option A. In cycle stealing mode, the DMA controller steals one bus cycle to transfer one word (or block) of data at a time, then returns the bus to the CPU. This statement is TRUE.

Step 2: Analyze Option B. In burst mode, the DMA controller transfers an entire block of data in a single continuous burst, minimizing the overhead of repeated bus arbitration. Thus, burst mode has higher throughput for bulk data than cycle stealing. This statement is TRUE.

Step 3: Analyze Option C. Programmed I/O requires the CPU to execute a tight loop of instructions for every single byte transferred, keeping the CPU 100% busy with I/O. Interrupt-driven I/O allows the CPU to execute other instructions while waiting for the device, leading to much better CPU utilization. Therefore, the claim that Programmed I/O has better CPU utilization is FALSE.

Step 4: Analyze Option D. Vectored interrupts provide the address of the ISR directly on the data bus, saving the CPU from having to execute a generic polling routine to find the ISR address. Thus, the CPU starts the ISR faster. This statement is TRUE.

Answer: C

Question 5 · Computer Organization and Architecture · 2023 NAT

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes

100 μ s

(micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional

200 μ s

to process the keystroke. Let

T_{1}

denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let

T_{2}

denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio

\frac{T _{1}}{T _{2}}

is __________. (Rounded off to one decimal place)

Correct Answer:

10.2

Step-by-Step Solution

Key idea: This is an I/O overhead comparison question, asking to calculate and compare the CPU time fraction consumed by polling versus interrupt-driven I/O.

Step 1: Calculate $T_{1}$ (Polling overhead per second).

Polling interval = 10 ms = 0.01 seconds.
Number of polls per second = $1/0.01 = 100$ polls.
Time spent polling per second = $100 \times 100 \mu s = 10, 000 \mu s = 0.01$ seconds.
The keyboard is used at 1 keystroke per second. Processing time for this keystroke = $200 \mu s = 0.0002$ seconds.
Total $T_{1} = 0.01 + 0.0002 = 0.0102$ seconds.

Step 2: Calculate $T_{2}$ (Interrupt overhead per second).

1 keystroke per second triggers 1 interrupt.
Time per interrupt service and processing = 1 ms = 0.001 seconds.
Total $T_{2} = 0.001$ seconds.

Step 3: Calculate the ratio $T_{1} / T_{2}$ .

Ratio = $0.0102/0.001 = 10.2$ .

Answer: 10.2

Question 6 · Computer Organization and Architecture · 2022 MCQ

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

A.
DMA based I/O transfer
B.
Interrupt driven I/O transfer
C.
Polling based I/O transfer
D.
Programmed I/O transfer

Correct Answer:

Step-by-Step Solution

Key idea: This is a conceptual comparison question about I/O transfer mechanisms, recognisable because it asks for the "highest throughput" for "bulk data" among standard I/O techniques.

Step 1: Evaluate Programmed I/O. The CPU must execute a sequence of instructions for every single byte or word transferred. This keeps the CPU 100% occupied with the transfer, resulting in the lowest throughput.

Step 2: Evaluate Polling. Similar to programmed I/O, the CPU continuously checks the device status in a loop, wasting even more cycles when the device is not ready. Throughput remains very low.

Step 3: Evaluate Interrupt-driven I/O. The CPU can do other work while waiting for the device. However, when the device is ready, the CPU still must execute instructions to move each byte from the device interface to memory.

Step 4: Evaluate DMA (Direct Memory Access). The DMA controller takes over the system bus and transfers entire blocks of data directly between the device and main memory without CPU intervention. The CPU is only involved at the start and end. This minimizes overhead and maximizes data transfer rate.

Answer: A

Question 7 · Computer Organization and Architecture · 2021_Set2 NAT

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.

Correct Answer:

80000

Step-by-Step Solution

Key idea: This is a DMA throughput calculation question, recognisable because it gives processor frequency, cycle fraction, and transfer size.

Step 1: Calculate the total number of CPU cycles per second. The processor is 2 MHz, which is $2 \times 1 0^{6}$ cycles/second.

Step 2: Calculate the number of cycles used for DMA per second. This is 0.5% of the total cycles: $0.005 \times 2 \times 1 0^{6} = 10, 000$ cycles/second.

Step 3: Relate cycles to data transferred. The problem states that 1 CPU cycle transfers one 8-bit character.

Step 4: Calculate the total data transfer rate in bits per second. $10, 000 cycles/sec \times 8 bits/cycle = 80, 000$ bits/second.

Answer: 80000

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Input-Output, Interrupts and DMA PYQs for GATE CS

Chapter Roadmap: Input-Output, Interrupts and DMA

Chapter Roadmap

Interrupt Processing and Priority Mechanisms

Interrupt Processing and Priority Mechanisms

Input-Output, Interrupts and DMA: Solved Questions with Step-by-Step Explanations (7 Problems)

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

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