Instruction Set, Datapath and Memory Organization PYQs for GATE CS

Solve 11+ Instruction Set, Datapath and Memory Organization previous year questions for GATE CS with answers and detailed solutions. Free sample questions below.

Chapter Roadmap: Instruction Set, Datapath and Memory Organization

1. Instruction Set Architecture and Encoding

The hardware-software contract. Instruction formats, opcode calculation, and expanding opcode techniques. (High Importance)

2. Addressing Modes and Effective Address

How the processor finds the operand: Immediate, Direct, Indirect, Register, and Indexed modes.

3. Load-Store Architecture and Assembly

Translating high-level language statements into sequences of load, compute, and store instructions.

4. Memory Block Organization and Decoding

Chip select logic, memory interleaving, and mapping address lines to physical memory blocks.

5. Processor Datapath and Operand Selection

The physical execution: ALU, multiplexers, register files, and control signals working in harmony.

Topic Hero: Instruction Set Architecture as the Hardware-Software Contract

The Instruction Set Architecture (ISA) is the abstract model of a computer that serves as the boundary between software and hardware. It is the complete specification of everything a programmer needs to know to write machine-level code that the processor can execute.

What IS part of the ISA:

Instruction Formats: Layout of bits (opcode, operand fields).
Data Types: Supported sizes (e.g., 32-bit integers, IEEE 754).
Registers: Number, size, and purpose of visible registers.
Addressing Modes: Rules for calculating effective addresses.
I/O Mechanisms: Processor communication with external devices.

What is NOT part of the ISA (Microarchitecture):

Clock frequency or cycle time.
Cache memory size and associativity.
The number of pipeline stages.
Specific physical logic gates used to implement the ALU.

Exam Principle: If a feature is visible to the assembly language programmer or the compiler, it is part of the ISA. If it is hidden and only affects performance, it is microarchitecture.

Instruction Set, Datapath and Memory Organization: Solved Questions with Step-by-Step Explanations (10 Problems)

Question 1 · Computer Organization and Architecture · 2026_Set2 MCQ

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

A.
8
B.
4
C.
64
D.
16

Correct Answer:

Step-by-Step Solution

Key idea: This is an expanding opcode instruction encoding question, recognisable by the mention of "variable-sized opcodes" and multiple instruction types with different operand counts.

Why this method applies: In expanding opcode techniques, unused opcode patterns from a shorter opcode field are "expanded" into longer opcode fields by sacrificing operand bits. We must track the number of available patterns at each stage.

Step 1: Analyze the base constraints.

Total instruction length = 2 bytes = 16 bits.

Number of registers = 16. Bits per register field = $lo g_{2} (16) = 4$ bits.

Step 2: Analyze M-type instructions.

Format: Opcode + 2 Register operands + 6-bit immediate.

Operand bits = $4 + 4 + 6 = 14$ bits.

Opcode bits = $16 - 14 = 2$ bits.

Total possible 2-bit patterns = $2^{2} = 4$ .

M-type uses 2 opcodes.

Remaining patterns for expansion = $4 - 2 = 2$ .

Step 3: Analyze R-type instructions.

Format: Opcode + 3 Register operands.

Operand bits = $4 + 4 + 4 = 12$ bits.

Opcode bits = $16 - 12 = 4$ bits.

Each of the 2 remaining 2-bit patterns can be expanded into $2^{2} = 4$ four-bit patterns.

Total available 4-bit patterns = $2 \times 4 = 8$ .

R-type uses 7 opcodes.

Remaining patterns for expansion = $8 - 7 = 1$ .

Step 4: Analyze C-type instructions.

Format: Opcode + 1 Register operand + 6-bit offset.

Operand bits = $4 + 6 = 10$ bits.

Opcode bits = $16 - 10 = 6$ bits.

The 1 remaining 4-bit pattern can be expanded into $2^{2} = 4$ six-bit patterns.

Total available 6-bit patterns = $1 \times 4 = 4$ .

Therefore, the maximum number of unique C-type opcodes is 4.

Answer: Option B.

Question 2 · Computer Organization and Architecture · 2026_Set1 MCQ

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

List I	List II
P. Immediate	1. Element of an array
Q. Indirect	2. Pointer
R. Base with index	3. Element of a record
S. Base with offset/displacement	4. Constant

A.
P–4, Q–3, R–1, S–2
B.
P–4, Q–2, R–1, S–3
C.
P–1, Q–4, R–3, S–2
D.
P–2, Q–3, R–1, S–4

Correct Answer:

Step-by-Step Solution

Key idea: This is a concept mapping question, recognisable because it asks to link hardware-level addressing modes with software-level data structures. The method is to analyse the components of each addressing mode and match them to how high-level languages access data.

Step 1: Analyse Immediate addressing. The operand is directly given in the instruction itself. This corresponds to a literal constant in code. So, P matches 4.

Step 2: Analyse Indirect addressing. The instruction gives the address of the address (or a register contains the address of the operand). This is the exact definition of a pointer (a variable that stores the memory address of another variable). So, Q matches 2.

Step 3: Analyse Base with index addressing. The effective address is Base + Index. The base is the start of a collection, and the index is a variable offset (like a loop counter). This is used to access elements of an array. So, R matches 1.

Step 4: Analyse Base with offset/displacement addressing. The effective address is Base + fixed Offset. The base is the start of a data structure, and the offset is a fixed distance to a specific field. This is used to access elements of a record or struct. So, S matches 3.

Conclusion: P-4, Q-2, R-1, S-3. This matches option B.

Question 3 · Computer Organization and Architecture · 2026_Set1 MCQ

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement

Z = X + Y

?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

A.
ADD Z, X, Y
B. LOAD R0, X
ADD Z, R0, Y
C. ADD R0, X, Y
STORE Z, R0
D. LOAD R0, X
LOAD R1, Y
ADD R2, R0, R1
STORE Z, R2

Correct Answer:

Step-by-Step Solution

Key idea: This is a load-store architecture translation question, recognisable because it asks to map a high-level variable assignment to a sequence of assembly instructions under strict memory-access rules.

Why this method applies: In a load-store architecture, the ALU cannot operate directly on memory operands. Data must be explicitly moved into registers before computation, and the result must be stored back to memory.

Step 1: Identify the operands. X and Y are memory operands, and Z is the memory destination.

Step 2: Load the operands into registers. We need two LOAD instructions to bring X and Y into registers (e.g., R0 and R1).

Step 3: Perform the computation. Use an ADD instruction with register operands to compute X + Y, storing the result in a third register (e.g., R2).

Step 4: Store the result. Use a STORE instruction to write the value from R2 back to the memory location Z.

Matching this sequence to the options:

Option A attempts a memory-memory ADD, which is invalid in load-store architecture.

Option B loads X but tries to ADD with Y still in memory, which is invalid.

Option C attempts to ADD memory operands directly, which is invalid.

Option D correctly loads X into R0, loads Y into R1, adds them into R2, and stores R2 into Z.

Answer: Option D.

Question 4 · Computer Organization and Architecture · 2025_Set2 MSQ

Which of the following is/are part of an Instruction Set Architecture of a processor?

A.
The size of the cache memory
B.
The clock frequency of the processor
C.
The number of cache memory levels
D.
The total number of registers

Correct Answer:

["D"]

Step-by-Step Solution

Key idea: This is an Instruction Set Architecture (ISA) definition question, recognisable because it asks to distinguish between architectural specifications and microarchitectural implementation details.

Why this method applies: The ISA is the contract between hardware and software. It defines everything a programmer (or compiler) must know to write correct machine code. Implementation details that are transparent to the programmer are not part of the ISA.

Step 1: Analyze "The size of the cache memory".

Cache size affects performance but is completely transparent to the instruction set. A program runs correctly regardless of cache size. This is a microarchitectural detail.

Step 2: Analyze "The clock frequency of the processor".

Clock frequency determines execution speed, not the set of valid instructions or programmer-visible state. This is a microarchitectural detail.

Step 3: Analyze "The number of cache memory levels".

Like cache size, the cache hierarchy (L1, L2, L3) is an implementation detail hidden from the ISA.

Step 4: Analyze "The total number of registers".

The number of architectural registers (e.g., 16 or 32 general-purpose registers) directly dictates the instruction format (how many bits are needed for register fields) and is explicitly visible to the assembly programmer. This is a fundamental part of the ISA.

Answer: Option D.

Question 5 · Computer Organization and Architecture · 2025_Set1 MSQ

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

A.
The data path can implement arithmetic operations involving two registers.
B.
The data path can implement arithmetic operations involving one register and one immediate value.
C.
The data path can implement arithmetic operations involving two immediate values.
D.
The data path can only implement arithmetic operations involving one register and one immediate value.

Correct Answer:

["A","B","C"]

Step-by-Step Solution

Key idea: This is a processor datapath analysis question, recognisable by the diagram showing registers, multiplexers, and an ALU, asking what operations are supported. Why this method applies: We must trace the possible data flows from the inputs (registers and immediate values) through the multiplexers to the ALU inputs. Step 1: Analyze the inputs to Mux_A. The diagram shows Mux_A has two inputs: the register RA and a 32-bit immediate value. Therefore, the first operand to the ALU can be either a register value or an immediate value. Step 2: Analyze the inputs to Mux_B. The diagram shows Mux_B has two inputs: the register RB and a 32-bit immediate value. Therefore, the second operand to the ALU can also be either a register value or an immediate value. Step 3: Evaluate the combinations. Since Mux_A and Mux_B operate independently, we can select any combination of their inputs: - Case 1: Select RA for Mux_A and RB for Mux_B. This implements arithmetic operations involving two registers. (Option A is correct). - Case 2: Select RA for Mux_A and immediate for Mux_B (or vice versa). This implements arithmetic operations involving one register and one immediate value. (Option B is correct). - Case 3: Select immediate for Mux_A and immediate for Mux_B. This implements arithmetic operations involving two immediate values. (Option C is correct). Step 4: Evaluate Option D. Option D states the datapath can only implement operations with one register and one immediate. This is false, as we just proved it can do Reg+Reg and Imm+Imm as well. Answer: Options A, B, and C.

Question 6 · Computer Organization and Architecture · 2025_Set1 MCQ

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25 // R1 = R1 + 25

A.
16
B.
20
C.
22
D.
24

Correct Answer:

Step-by-Step Solution

Key idea: This is an instruction format bit-budget question, recognisable by the total instruction size, number of registers, and number of instruction types.

Why this method applies: We must allocate the fixed 32-bit instruction length among the opcode, register operand, and immediate operand fields based on the hardware constraints provided.

Step 1: Identify the total instruction size.

Total bits = 32.

Step 2: Calculate the bits required for the opcode field.

The processor supports 50 distinct instruction types.

Bits needed = $⌈ lo g_{2} (50)⌉ = 6$ bits. (Since $2^{5} = 32$ is too small, and $2^{6} = 64$ is sufficient).

Step 3: Calculate the bits required for the register operand field.

The processor has 64 general-purpose registers.

Bits needed = $lo g_{2} (64) = 6$ bits.

Step 4: Analyze the instruction format.

The example ADD R1, #25 shows a two-operand instruction: one register operand (R1) and one immediate operand (#25).

Therefore, the instruction format consists of: Opcode + One Register Field + Immediate Field.

Step 5: Calculate the remaining bits for the immediate operand.

Immediate bits = Total bits - Opcode bits - Register bits

Immediate bits = 32 - 6 - 6 = 20 bits.

Answer: Option B (20).

Question 7 · Computer Organization and Architecture · 2024_Set2 NAT

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:

I-type Instruction Format:

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let

X

be the number of bits used to encode the UNUSED field,

Y

be the number of bits used to encode the OPCODE field, and

Z

be the number of bits used to encode the immediate value/address field. The value of

X + 2 Y + Z

is __________

Correct Answer:

Step-by-Step Solution

Key idea: This is a fixed-length instruction encoding question with an expanding/split opcode, recognisable by the instruction format diagrams and the request to find bit field sizes.

Why this method applies: We must use the "bit budget" method. The total instruction length is fixed at 32 bits. We can determine the size of each field by calculating the minimum bits required to represent the given number of options, then subtracting from 32.

Step 1: Determine the OPCODE field size ( $Y$ ).

There are 150 distinct instructions, equally divided into R-type and I-type.

This means there are 75 R-type instructions and 75 I-type instructions.

The problem states: "1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation."

To encode 75 distinct operations, we need $⌈ lo g_{2} (75)⌉ = 7$ bits.

Therefore, the total OPCODE field size is $Y = 1 (type bit) + 7 (operation bits) = 8$ bits.

Step 2: Determine the Register field size.

The processor has 50 architectural registers.

To uniquely identify one register, we need $⌈ lo g_{2} (50)⌉ = 6$ bits.

All register fields are of equal size, so each is 6 bits.

Step 3: Calculate the UNUSED field size ( $X$ ) for R-type.

R-type format: OPCODE + UNUSED + DST Register + SRC Register1 + SRC Register 2 = 32 bits.

Substitute the known sizes: $8 + X + 6 + 6 + 6 = 32$ .

$8 + X + 18 = 32 ⟹ X + 26 = 32 ⟹ X = 6$ bits.

Step 4: Calculate the Immediate field size ( $Z$ ) for I-type.

I-type format: OPCODE + DST Register + SRC Register + Immediate = 32 bits.

Substitute the known sizes: $8 + 6 + 6 + Z = 32$ .

$20 + Z = 32 ⟹ Z = 12$ bits.

Step 5: Compute the final expression.

We need the value of $X + 2 Y + Z$ .

$X + 2 Y + Z = 6 + 2 (8) + 12 = 6 + 16 + 12 = 34$ .

Answer: 34.

Question 8 · Computer Organization and Architecture · 2024_Set2 NAT

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is __________

Correct Answer:

Step-by-Step Solution

Key idea: This is a fixed-length instruction encoding question, recognisable by the total instruction size and the explicit list of required bit fields.

Why this method applies: The total number of bits in an instruction is fixed. We can determine the size of the opcode field by subtracting the bits required for all other specified fields from the total instruction length.

Step 1: Identify the total instruction size.

Total bits = 32.

Step 2: Calculate the bits required for each specified field.

Two register operand fields: The processor has 16 general-purpose registers. To uniquely identify one register, we need log2(16) = 4 bits. Since there are two such fields, this requires 2 * 4 = 8 bits.
Addressing mode field: The processor supports 8 addressing modes. To uniquely identify one mode, we need log2(8) = 3 bits.
Scalar field: The problem explicitly states this field is 16 bits.

Step 3: Sum the bits used by these fields.

Total used bits = 8 (registers) + 3 (addressing mode) + 16 (scalar) = 27 bits.

Step 4: Calculate the remaining bits for the opcode field.

Opcode bits = Total bits - Used bits = 32 - 27 = 5 bits.

Step 5: Determine the maximum number of unique opcodes.

With 5 bits, we can represent 2^5 = 32 unique combinations.

Answer: 32.

Question 9 · Computer Organization and Architecture · 2023 MCQ

Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.

//C-code

int a[10], b[10], i;
// int is 32-bit
for (i=0; i<10;i++)
   a[i] = b[i] * 8;

;assembly-code (; indicates comments)
;r1-r5 are 32-bit integer registers
;initialize r1=0, r2=10
;initialize r3, r4 with base address of a, b

L01: jeq r1, r2, end    ;if(r1==r2) goto end
L02: lw r5, 0(r4)        ;r5 <- Memory[r4+0]
L03: shl r5, r5, U1      ;r5 <- r5 << U1
L04: sw r5, 0(r3)        ;Memory[r3+0] <- r5
L05: add r3, r3, U2      ;r3 <- r3+U2
L06: add r4, r4, U3
L07: add r1, r1, 1
L08: jmp U4            ;goto U4
L09: end

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

A.
(8, 4, 1, L02)
B.
(3, 4, 4, L01)
C.
(8, 1, 1, L02)
D.
(3, 1, 1, L01)

Correct Answer:

Step-by-Step Solution

Key idea: This is an assembly translation and tracing question, recognisable by the side-by-side C code and assembly with missing operands (U1–U4).

Why this method applies: We must map the high-level array operation a[i] = b[i] * 8 to the low-level load-store assembly, paying close attention to data sizes (byte addressing) and loop control flow.

Step 1: Analyze the multiplication.

The C code multiplies b[i] by 8. In assembly, shl r5, r5, U1 performs a left shift. Shifting left by $k$ is equivalent to multiplying by $2^{k}$ .

Since $8 = 2^{3}$ , we must shift left by 3. Therefore, U1 = 3.

Step 2: Analyze the array pointer increments.

The arrays a and b are of type int, which is 32-bit (4 bytes).

The memory is byte-addressable. To move to the next element in the array, the base address pointer must be incremented by the size of one element in bytes.

Therefore, both r3 (base of a) and r4 (base of b) must be incremented by 4.

This means U2 = 4 and U3 = 4.

Step 3: Analyze the loop control flow.

The loop condition i < 10 is checked at label L01 (jeq r1, r2, end).

After incrementing the pointers and the loop counter i (add r1, r1, 1), the program must jump back to the beginning of the loop to re-evaluate the condition.

Therefore, the jump target U4 must be L01.

Step 4: Combine the findings.

(U1, U2, U3, U4) = (3, 4, 4, L01).

Answer: Option B.

Question 10 · Computer Organization and Architecture · 2023 MCQ

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

A.
(0, 1, 2, 3)
B.
(0, 1024, 2048, 3072)
C.
(0, 8, 16, 24)
D.
(0, 0, 0, 0)

Correct Answer:

Step-by-Step Solution

Key idea: This is a memory address decoding question, recognisable by the use of a decoder to generate Chip Select (CS) signals for multiple memory blocks. Why this method applies: We must determine the starting address of each memory block by analyzing which address lines are connected to the decoder (for block selection) and which are connected directly to the memory blocks (for intra-block addressing). Step 1: Understand the total address space. The total memory is 4 KB, which is

4 \times 1024 = 4096

bytes. This requires

lo g_{2} (4096) = 12

address lines, labeled IA11 (MSB) to IA0 (LSB). Step 2: Identify the block size and its address requirements. Each block is 1 KB (

1024

bytes), requiring

lo g_{2} (1024) = 10

address lines. Step 3: Identify the address lines connected to the blocks. The problem states that ten input address lines are connected to the address port of the blocks. Based on the diagram and description, these are IA11–IA5 (7 lines) and IA2–IA0 (3 lines). For the starting location (offset 0) of any block, all 10 of these address lines must be 0. Step 4: Identify the decoder input lines. The remaining two address lines, IA4 and IA3, are connected to the decoder inputs (A1 and A0, respectively). These lines determine which of the four blocks is selected. Step 5: Calculate the decimal address for each block's starting location. We set the 10 block address lines to 0, and vary the decoder inputs (IA4, IA3) to select each block (Q0 to Q3). - Block 1 (X1, Q0): Decoder input 00

\to

IA4=0, IA3=0. Binary address: `0000000 00 000`

\to

Decimal: 0. - Block 2 (X2, Q1): Decoder input 01

\to

IA4=0, IA3=1. Binary address: `0000000 01 000`

\to

Decimal:

2^{3} = 8

. - Block 3 (X3, Q2): Decoder input 10

\to

IA4=1, IA3=0. Binary address: `0000000 10 000`

\to

Decimal:

2^{4} = 16

. - Block 4 (X4, Q3): Decoder input 11

\to

IA4=1, IA3=1. Binary address: `0000000 11 000`

\to

Decimal:

2^{4} + 2^{3} = 16 + 8 = 24

. The starting locations are 0, 8, 16, and 24. Answer: Option C.

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Instruction Set, Datapath and Memory Organization PYQs for GATE CS

Chapter Roadmap: Instruction Set, Datapath and Memory Organization

Topic Hero: Instruction Set Architecture as the Hardware-Software Contract

What IS part of the ISA:

What is NOT part of the ISA (Microarchitecture):

Instruction Set, Datapath and Memory Organization: Solved Questions with Step-by-Step Explanations (10 Problems)

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