Cache Memory, Memory Hierarchy and Address Translation PYQs for GATE CS

Solve 18+ Cache Memory, Memory Hierarchy and Address Translation previous year questions for GATE CS with answers and detailed solutions. Free sample questions below.

Chapter Roadmap: Cache Memory and Memory Hierarchy

Your Journey Through Cache Memory

Topic 1: Direct-Mapped Cache Addressing

Address decomposition: Tag, Index, Offset. Simple one-to-one mapping. Foundation for all cache concepts.

Topic 2: Set-Associative Cache

K-way associativity. Trade-off between direct-mapped and fully associative. More flexible placement.

Topic 3: Access Sequences and Conflict Misses

Sequential access patterns. Conflict vs capacity misses. Real exam traps.

Topic 4: Write Policies and Replacement

Write-through vs write-back. Write-allocate vs no-write-allocate. LRU and other replacement algorithms.

Topic 5: Cache Performance

Hit rate, miss rate, miss penalty. Effective memory access time (EMAT). Multi-level cache (L1, L2).

Topic 6: TLB and Virtual Memory Integration

Address translation. Cache and TLB interaction. Complete system view.

What you will master by the end:

Calculate tag, index, offset bits for any cache configuration
Analyze cache performance and hit rates
Understand conflict misses and replacement policies
Solve multi-level cache problems
Connect cache with virtual memory systems

What is a Direct-Mapped Cache?

The Core Idea

A direct-mapped cache is the simplest cache organization where each memory block maps to exactly one specific cache line.

Cache Line = B mod N

Where $B$ is block number and $N$ is number of lines

Why This Matters

Fast lookup: Hardware checks only one location
Simple design: Minimal comparison logic needed
Conflict problem: Two different memory blocks may compete for the same cache line

Visual Intuition

Main MemoryCache

Block 0→ Line 0

Block 1→ Line 1

Block 2→ Line 2

Block 3→ Line 3

Block 4→ Line 0 (conflict)

Block 5→ Line 1 (conflict)

Key takeaway: One memory block has one home in the cache. No choices, no flexibility.

Cache Memory, Memory Hierarchy and Address Translation: Solved Questions with Step-by-Step Explanations (10 Problems)

Question 1 · Computer Organization and Architecture · 2026_Set2 NAT

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number

17 6_{10}

. The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer)

Note:

1 K = 2^{10}

and

1 M = 2^{20}

Correct Answer:

128.00

Step-by-Step Solution

Insight: This is a reverse-engineering problem — extract the index field from the address by matching the given cache block number, then maximise the index width.

Exam route:

Address = 0xA2C28 = 1010 0010 1100 0010 1000 (20 bits). Block number = 176.
In direct-mapped cache, cache block number = index field of the address.
Try offset = 6 (block = 64 B): address >> 6 = 10416. $10416 mod 256 = 176$ ✓.
Maximise index: $10416 mod 2^{11} = 10416 mod 2048 = 176$ ✓. $10416 mod 2^{12} = 10416 mod 4096 = 2224 \neq = 176$ ✗.
Max index = 11 bits. Cache = $2^{11} \times 2^{6} = 2^{17}$ B = 128 KB.

Answer: 128

Learning route:

This is a reverse-engineering question, recognisable because it gives a specific address and the cache block it maps to, and asks for the maximum cache size.

In a direct-mapped cache, the cache block number equals the index field of the address. So we need to find offset and index bits such that the index field of 0xA2C28 equals 176.

Step 1 — Convert to binary: 0xA2C28 = 1010 0010 1100 0010 1000 (20 bits).

Step 2 — The address splits as [Tag | Index | Offset]. If offset = $k$ bits, then the index value is $⌊ address / 2^{k} ⌋ mod 2^{index_bits}$ .

Step 3 — Try offset = 6 (block = 64 B): $⌊ 666664/64 ⌋ = 10416$ . Check: $10416 mod 256 = 176$ ✓. So offset = 6, and 8 index bits gives block 176.

Step 4 — Maximise index bits. We need $10416 mod 2^{n} = 176$ .

$n = 9$ : $10416 mod 512 = 176$ ✓
$n = 10$ : $10416 mod 1024 = 176$ ✓
$n = 11$ : $10416 mod 2048 = 176$ ✓
$n = 12$ : $10416 mod 4096 = 2224 \neq = 176$ ✗

Maximum index = 11 bits.

Step 5 — Cache size = $2^{11} \times 2^{6} = 2^{17}$ B = 128 KB.

Check: Tag = $20 - 11 - 6 = 3$ bits ≥ 1 ✓. Cache (128 KB) < Memory (1 MB) ✓.

Note: The smart_notes worked example (card c007) uses a heuristic offset of 4 based on the last nibble, which gives 512 KB — but that is incorrect because with offset = 4, the index would be $41666 mod 256 = 194 \neq = 176$ . The correct offset is 6, giving 128 KB.

Question 2 · Computer Organization and Architecture · 2026_Set2 MSQ

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,…

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).

P : 0 x 845 B 32, Q : 0 x 845 B 26, R : 0 x 845 B 36, S : 0 x 846 B 32

Which of the following statements is/are true?

Note:

1 K = 2^{10}

and

1 M = 2^{20}

A.
Every access to P results in a cache miss
B.
Every access to R results in a cache hit
C.
Every access to Q results in a cache miss
D.
Except the first access to S, all subsequent accesses to S result in cache hits

Correct Answer:

["A","B"]

Step-by-Step Solution

Key idea: this is a cache access sequence tracing question, recognisable because it gives specific hex addresses and a repeating access pattern, requiring you to map each address to a cache line and track hits/misses over multiple rounds.

Step 1: Determine the cache parameters. Cache size = 4 KB = $2^{12}$ bytes. Block size = 16 bytes = $2^{4}$ bytes. Number of lines = $2^{12} / 2^{4} = 2^{8} = 256$ . Index bits = 8. Offset bits = 4.

Step 2: Extract the index and tag for each address. The offset is the last 4 bits (1 hex digit). The index is the next 8 bits (2 hex digits). The tag is the remaining bits.

P (0x845B32): Offset = 2, Index = B3, Tag = 845.
Q (0x845B26): Offset = 6, Index = B2, Tag = 845.
R (0x845B36): Offset = 6, Index = B3, Tag = 845.
S (0x846B32): Offset = 2, Index = B3, Tag = 846.

Step 3: Notice that P and R have the exact same Tag and Index. They map to the same cache block. Q maps to line B2. S maps to line B3 but has a different tag (846).

Step 4: Trace the sequence P, Q, R, S for Round 1:

P: Line B3 miss. Loads block (Tag 845).
Q: Line B2 miss. Loads block (Tag 845).
R: Line B3 hit. (Block is already there from P).
S: Line B3 miss. Loads block (Tag 846), evicting P/R.

Step 5: Trace Round 2 and beyond:

P: Line B3 miss (evicts S).
Q: Line B2 hit (never evicted).
R: Line B3 hit (loaded by P in this round).
S: Line B3 miss (evicts P/R).

Step 6: Evaluate the options. P always misses (True). R always hits (True). Q misses first, then hits (False). S always misses (False).

Answer: A, B

Question 3 · Computer Organization and Architecture · 2026_Set1 MCQ

The size of the physical address space of a processor is

2^{32}

bytes. The capacity of a cache memory unit is

2^{23}

bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a

K

-way set-associative cache, where

K = 2^{L}

and

L \in {1, 2, 3}

. Let the length of the TAG field be

M

bits for the direct mapped cache, and

N

bits for the set-associative cache.

Which one of the following options is true?

A.
$N = M + L$
B.
$N = M - L$
C.
$N = M + K$
D.
$N = M - K$

Correct Answer:

Step-by-Step Solution

Insight: This is a tag-length comparison question between direct-mapped and set-associative caches. The key is to express the tag bits for both configurations in terms of the given parameters and find the relationship.

Exam route:

Physical address = 32 bits. Block size = 128 = $2^{7}$ bytes $⟹$ Offset = 7 bits.
Cache capacity = $2^{23}$ bytes.
Direct-mapped (K=1): Lines = $2^{23} / 2^{7} = 2^{16}$ . Index = 16 bits. Tag M = $32 - 16 - 7 = 9$ bits.
Set-associative (K= $2^{L}$ ): Sets = $2^{16} / 2^{L} = 2^{16 - L}$ . Index = $16 - L$ bits. Tag N = $32 - (16 - L) - 7 = 9 + L$ bits.
Since M = 9, we have N = M + L.

Answer: A

Learning route:

This question is recognisable because it gives cache parameters and asks for the mathematical relationship between the tag lengths of a direct-mapped cache and a K-way set-associative cache.

Let's derive the tag lengths step-by-step:

Common parameters: Address = 32 bits. Block size = 128 bytes $⟹$ Offset = $lo g_{2} (128) = 7$ bits. Cache capacity = $2^{23}$ bytes.
Direct-mapped cache (M): Associativity K = 1. Number of lines = Cache / Block = $2^{23} / 2^{7} = 2^{16}$ . Index bits = $lo g_{2} (2^{16}) = 16$ . Tag bits M = Address - Index - Offset = $32 - 16 - 7 = 9$ bits.
Set-associative cache (N): Associativity K = $2^{L}$ . Number of sets = Lines / K = $2^{16} / 2^{L} = 2^{16 - L}$ . Index bits = $lo g_{2} (2^{16 - L}) = 16 - L$ . Tag bits N = Address - Index - Offset = $32 - (16 - L) - 7 = 9 + L$ bits.
Relationship: We know M = 9. Substituting this into N gives N = M + L.

Common wrong path: Students often miscalculate the number of sets in the set-associative cache by forgetting to divide by K, or they confuse the number of lines with the number of sets. If you forget to divide by K, you get Index = 16, leading to N = 9, which would imply N = M (not an option). Always carefully distinguish between lines and sets.

Generalization: When comparing tag lengths, increasing associativity by a factor of K reduces the index bits by $lo g_{2} (K)$ , which directly increases the tag bits by $lo g_{2} (K)$ .

Verification: Let L = 2 (4-way). Sets = $2^{16} /4 = 2^{14}$ . Index = 14. N = $32 - 14 - 7 = 11$ . M + L = 9 + 2 = 11. Matches perfectly.

Question 4 · Computer Organization and Architecture · 2026_Set1 MSQ

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

A.
TLB miss, Page table hit, Cache hit
B.
TLB hit, Page table miss, Cache hit
C.
TLB miss, Page table miss, Cache hit
D.
TLB miss, Page table miss, Cache miss

Correct Answer:

["B","C"]

Step-by-Step Solution

Insight: This is a sequence-of-events question testing the logical dependencies between the TLB, page table, and cache. The key is to recognize that a TLB hit guarantees the page is in main memory, and a page table miss guarantees the page is not in main memory (and thus not in the cache).

Exam route:

TLB hit implies the translation is in the TLB, meaning the page is currently in main memory. Therefore, a "Page table miss" (page not in memory) contradicts a TLB hit. Sequence B can NEVER happen.
Page table miss implies the page is not in main memory (page fault). The problem states that when a page is evicted, its cache blocks are marked invalid. Thus, a cache hit is impossible. Sequence C can NEVER happen.
Sequence A (TLB miss, Page table hit, Cache hit) is a standard valid sequence where the translation is fetched from memory and the data is already in the cache.
Sequence D (TLB miss, Page table miss, Cache miss) is a standard page fault sequence.

Answer: B, C

Learning route:

This question is recognisable because it lists sequential events involving the MMU and cache, asking which combination is logically impossible.

Let's trace the rules of the memory hierarchy:

The TLB is a cache for the page table. If there is a TLB hit, the page is valid and in main memory. We do not even access the page table. Thus, "TLB hit" and "Page table miss" are mutually exclusive. This makes B impossible.
If there is a Page table miss, the page is not in main memory. The problem explicitly states that evicted pages have their cache blocks invalidated. Therefore, the cache cannot possibly hit. This makes C impossible.
A and D represent normal cache hit and page fault scenarios, respectively.

Common wrong path: Students might think C is possible if they forget the problem's specific condition about cache invalidation upon page eviction. Without that condition, one might wrongly assume stale cache data could cause a hit. Always read the problem's constraints carefully.

Generalization: TLB hit $⟹$ Page in memory. Page not in memory $⟹$ Cache miss (assuming proper invalidation).

Verification: If B were possible, the TLB would contain a translation for a page not in the page table, breaking the TLB's purpose as a page table cache. If C were possible, the cache would hit on a page not in memory, violating the invalidation rule.

Question 5 · Computer Organization and Architecture · 2025_Set2 MCQ

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.

Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?

A.
64 KB and 4 KB
B.
128 KB and 16 KB
C.
64 KB and 8 KB
D.
128 KB and 6 KB

Correct Answer:

Step-by-Step Solution

Key idea: this is a direct-mapped cache address decomposition question, recognisable because it gives the tag bits, index bits, and block size, and asks to reverse-engineer the main memory and cache sizes.

Step 1: Identify the given parameters. Tag bits = 4. Index bits = 12. Block size = 1 byte.

Step 2: Calculate the cache size. The number of index bits tells us the number of lines in the cache. Number of lines = $2^{12} = 4096$ . Since each block is 1 byte, the total cache size = $4096 \times 1$ byte = 4096 bytes = 4 KB.

Step 3: Calculate the main memory size. The total physical address size is the sum of Tag, Index, and Offset bits. Offset bits = $lo g_{2} (Block size) = lo g_{2} (1) = 0$ .

Total address bits = Tag + Index + Offset = $4 + 12 + 0 = 16$ bits.

Main memory size = $2^{16}$ bytes = 65536 bytes = 64 KB.

Step 4: Match with the options. Main memory = 64 KB, Cache = 4 KB.

Answer: A

Question 6 · Computer Organization and Architecture · 2025_Set2 NAT

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is ___________ . (rounded off to one decimal place)

Correct Answer:

4.0

Step-by-Step Solution

Key idea: This is a two-level hierarchical cache AMAT calculation. We must carefully interpret the given "miss penalty" phrases as the access times of the respective lower levels.

Step 1: Identify the given parameters.

L1 access time ( $T_{1}$ ) = 1 ns
L1 hit rate ( $H_{1}$ ) = 90% = 0.9 $⟹$ L1 miss rate ( $M_{1}$ ) = 0.1
L2 hit rate ( $H_{2}$ ) = 80% = 0.8 $⟹$ L2 miss rate ( $M_{2}$ ) = 0.2
"Miss penalty for transferring data from L2 cache to L1 cache" = 10 ns. This is the time taken when L1 misses, which is the L2 access time ( $T_{2}$ ). So, $T_{2} = 10$ ns.
"Miss penalty for the data to be transferred from main memory to L2 cache" = 100 ns. This is the time taken when L2 misses, which is the Main Memory access time ( $T_{3}$ ). So, $T_{3} = 100$ ns.

Step 2: Apply the hierarchical AMAT formula.

$A M A T = T_{1} + M_{1} \times (T_{2} + M_{2} \times T_{3})$

Step 3: Substitute the values.

$A M A T = 1 + 0.1 \times (10 + 0.2 \times 100)$

$A M A T = 1 + 0.1 \times (10 + 20)$

$A M A T = 1 + 0.1 \times 30$

$A M A T = 1 + 3$

$A M A T = 4$ ns

Step 4: Format the answer.

The question asks for the answer rounded off to one decimal place.

Answer: 4.0

Question 7 · Computer Organization and Architecture · 2025_Set1 MCQ

Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, $1 K = 2^{10}$ , $1 M = 2^{20}$ .]

A.
$6 \times 2^{10}$
B.
$8 \times 2^{10}$
C.
$2^{12}$
D.
$2^{14}$

Correct Answer:

Step-by-Step Solution

Insight: This is a two-part question — first find tag bits per line, then multiply by the number of lines to get total tag storage.

Exam route:

Cache = 16 KB = $2^{14}$ B, Block = 16 B = $2^{4}$ B, Address = 20 bits.
Lines = $2^{14} / 2^{4} = 2^{10}$ .
Index = 10, Offset = 4, Tag = $20 - 10 - 4 = 6$ bits.
Total tag bits = $6 \times 2^{10}$ .

Answer: A

Learning route:

This is a total-tag-memory question, recognisable because it asks "how many bits to store all the tag values" rather than just the tag field width.

Step 1 — Find tag bits per line using the four-step method:

Lines = $16 K /16 = 2^{14} / 2^{4} = 2^{10} = 1024$ .
Index = $lo g_{2} (1024) = 10$ bits.
Offset = $lo g_{2} (16) = 4$ bits.
Tag = $20 - 10 - 4 = 6$ bits per line.

Step 2 — Multiply by the number of lines:

Total tag storage = $6 \times 1024 = 6 \times 2^{10}$ bits.

Wrong path analysis:

Option B ( $8 \times 2^{10}$ ): Used Tag = 8, which comes from Offset = 2 (wrong block size interpretation).
Option C ( $2^{12} = 4 \times 2^{10}$ ): Used Tag = 4, which comes from forgetting to subtract offset ( $20 - 16 = 4$ ).
Option D ( $2^{14} = 16 \times 2^{10}$ ): Used Tag = 16, which comes from forgetting both index and offset.

Verification: $6 \times 2^{10} = 6144$ bits. With 1024 lines each storing a 6-bit tag, this is correct ✓.

Question 8 · Computer Organization and Architecture · 2025_Set1 NAT

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ________. (rounded off to two decimal places)

Correct Answer:

12.50

Step-by-Step Solution

Key idea: This is a hierarchical cache Average Memory Access Time (AMAT) calculation. We must use the given hit rates and access times (which include lower-level penalties) to compute the overall AMAT.

Step 1: Identify the given parameters.

L1 access time ( $T_{1}$ ) = 10 ns
L1 hit rate ( $H_{1}$ ) = 95% = 0.95 $⟹$ L1 miss rate ( $M_{1}$ ) = 0.05
L2 access time ( $T_{2}$ ) = 20 ns (given as "including L1 cache miss penalty", which is the standard definition of $T_{2}$ in the AMAT formula)
L2 hit rate ( $H_{2}$ ) = 85% = 0.85 $⟹$ L2 miss rate ( $M_{2}$ ) = 0.15
Main Memory access time ( $T_{3}$ ) = 200 ns (given as "including L1 and L2 cache miss penalty", which is $T_{3}$ )

Step 2: Apply the hierarchical AMAT formula.

$A M A T = T_{1} + M_{1} \times (T_{2} + M_{2} \times T_{3})$

Step 3: Substitute the values.

$A M A T = 10 + 0.05 \times (20 + 0.15 \times 200)$

$A M A T = 10 + 0.05 \times (20 + 30)$

$A M A T = 10 + 0.05 \times 50$

$A M A T = 10 + 2.5$

$A M A T = 12.5$ ns

Step 4: Format the answer.

The question asks for the answer rounded off to two decimal places.

Answer: 12.50

Question 9 · Computer Organization and Architecture · 2024_Set1 NAT

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is _________

Correct Answer:

3.00

Step-by-Step Solution

Key idea: this is a cache performance and AMAT (Average Memory Access Time) question, recognisable because it provides instruction mix, miss rates, and miss penalty, asking for the speedup of a perfect cache.

Step 1: Identify the given parameters. Ideal CPI = 2. Load/store fraction = 25% = 0.25. Instruction miss rate = 2% = 0.02. Data miss rate = 8% = 0.08. Miss penalty = 100 cycles.

Step 2: Calculate the stall cycles per instruction for the imperfect cache.

Instruction stalls per instruction = Miss rate $\times$ Penalty = $0.02 \times 100 = 2$ cycles.
Data stalls per instruction = Load/store fraction $\times$ Data miss rate $\times$ Penalty = $0.25 \times 0.08 \times 100 = 2$ cycles.

Step 3: Calculate the actual CPI with the imperfect cache.

Actual CPI = Ideal CPI + Instruction stalls + Data stalls = $2 + 2 + 2 = 6$ .

Step 4: Calculate the speedup. A perfect cache has 0 misses, so its CPI is just the ideal CPI = 2.

Speedup = Actual CPI / Perfect CPI = $6/2 = 3.00$ .

Answer: 3.00

Question 10 · Computer Organization and Architecture · 2024_Set1 MSQ

Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

A.
A read miss in WBC never evicts a dirty block
B.
A read miss in WTC never triggers a write back operation of a cache block to main memory
C.
A write hit in WBC can modify the value of the dirty bit of a cache block
D.
A write miss in WTC always writes the victim cache block to main memory before loading the missed block to the cache

Correct Answer:

["B","C"]

Step-by-Step Solution

Key idea: This is a cache write policy and replacement tracing question. We must evaluate each statement based on the rules of Write-Back Cache (WBC) and Write-Through Cache (WTC).

Step 1: Analyze Option A.

"A read miss in WBC never evicts a dirty block."

In WBC, blocks can be modified (dirty). If the cache is full and a read miss occurs, the LRU policy will select a victim. If the LRU block is dirty, it will be evicted (and written back to memory). Thus, it CAN evict a dirty block. Option A is False.

Step 2: Analyze Option B.

"A read miss in WTC never triggers a write back operation of a cache block to main memory."

In WTC, every write operation immediately updates both the cache and main memory. Therefore, no block in the cache is ever marked as dirty. When a block is evicted, it is already consistent with main memory, so no write-back is needed. Option B is True.

Step 3: Analyze Option C.

"A write hit in WBC can modify the value of the dirty bit of a cache block."

If a clean block (dirty bit = 0) in WBC receives a write hit, its data is updated in the cache, and the dirty bit is changed to 1 to indicate it is now dirty. Option C is True.

Step 4: Analyze Option D.

"A write miss in WTC always writes the victim cache block to main memory before loading the missed block to the cache."

As established in Step 2, WTC maintains memory consistency at all times. The victim block is never dirty. Therefore, it never needs to be written back to main memory upon eviction. Option D is False.

Answer: ["B", "C"]

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Cache Memory, Memory Hierarchy and Address Translation PYQs for GATE CS

Chapter Roadmap: Cache Memory and Memory Hierarchy

Your Journey Through Cache Memory

What you will master by the end:

What is a Direct-Mapped Cache?

The Core Idea

Why This Matters

Visual Intuition

Cache Memory, Memory Hierarchy and Address Translation: Solved Questions with Step-by-Step Explanations (10 Problems)

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

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Step-by-Step Solution

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