Computer Organization and Architecture Practice Questions for GATE CS

GATE CS Computer Organization and Architecture: 6 chapters, 66 previous year questions (100% of Computer Organization and Architecture), 1032 practice questions and one solved question from each chapter.

About Computer Organization and Architecture Practice Questions

1032 practice questions for Computer Organization and Architecture in GATE CS, sorted chapter by chapter and graded from basic to exam level, each with a full solution.

Computer Organization and Architecture Weightage in GATE CS

Computer Organization and Architecture accounts for 66 of 66 Computer Organization and Architecture previous year questions in our bank (100%), about 6.6 per paper across 10 papers.

Computer Organization and Architecture Chapter Matrix

Chapter	Topics	PYQs	Share of unit PYQs	Practice questions
Number Representation and Computer Arithmetic	Signed Integer Representation and Arithmetic Overflow, Booth Multiplication Algorithm, IEEE 754 Encoding, Decoding and Special Values, IEEE 754 Floating-Point Arithmetic, Endianness and Byte Ordering	14	21%	198
Instruction Set, Datapath and Memory Organization	Instruction Set Architecture and Instruction Encoding, Addressing Modes and Effective Address Computation, Load-Store Architecture and Assembly Translation, Memory Block Organization and Address Decoding, Processor Datapath and Operand Selection	11	17%	192
Processor Performance, Pipelining and Hazards	Pipeline Timing, Latency and Throughput, Pipeline CPI, Clock Rate and Stall Performance, Data Dependencies, Hazards and Forwarding, Control Hazards and Branch Prediction, Parallel Speedup and Multicore Performance	13	20%	200
Cache Memory, Memory Hierarchy and Address Translation	Direct-Mapped Cache Addressing and Tag Calculation, Set-Associative Cache Organization and Associativity, Cache Access Sequences and Conflict Misses, Cache Write Policies, Allocation and Replacement, Cache Performance and Effective Memory Access Time, TLB, Virtual Memory and Cache Interaction	18	27%	274
Input-Output, Interrupts and DMA	Interrupt Processing and Priority Mechanisms, DMA Modes, Throughput and Bulk Data Transfer, Polling and I/O Processing Overhead	7	11%	121
Secondary Storage and Disk Performance	Disk Geometry, Capacity and Cylinders, Disk Access Time, Seek and Rotational Latency	3	5%	47

One Solved Question from Each Computer Organization and Architecture Chapter

Question 1 · Number Representation and Computer Arithmetic MCQ

Consider an $n$ -bit 2's complement adder computing $S = A + B$ . Let $A_{n - 1}$ and $B_{n - 1}$ be the sign bits of the operands, $S_{n - 1}$ be the sign bit of the result, $C_{n - 1}$ be the carry into the sign bit position, and $C_{n}$ be the carry out of the sign bit position.

Which of the following combinations of $(A_{n - 1}, B_{n - 1}, S_{n - 1}, C_{n - 1}, C_{n})$ is IMPOSSIBLE?

A.
$(0, 0, 1, 1, 0)$
B.
$(1, 1, 0, 0, 1)$
C.
$(0, 1, 1, 0, 0)$
D.
$(0, 0, 1, 0, 0)$

Correct Answer:

Step-by-Step Solution

Key idea: This is a hardware logic elimination question. You must use the fundamental full-adder equation at the Most Significant Bit (MSB) position to check the physical validity of each carry and sign bit combination.

Step 1: Write the addition equation for the MSB (bit $n - 1$ ).

The sum bit $S_{n - 1}$ and the carry out $C_{n}$ are determined by:

$A_{n - 1} + B_{n - 1} + C_{n - 1} = S_{n - 1} + 2 C_{n}$

where all variables are either 0 or 1.

Step 2: Test Option A: $(0, 0, 1, 1, 0)$

Substitute into the equation: $0 + 0 + 1 = 1 + 2 (0) ⟹ 1 = 1$ .

This is mathematically valid. (This represents Pos + Pos = Neg, an overflow condition).

Step 3: Test Option B: $(1, 1, 0, 0, 1)$

Substitute: $1 + 1 + 0 = 0 + 2 (1) ⟹ 2 = 2$ .

This is mathematically valid. (This represents Neg + Neg = Pos, an overflow condition).

Step 4: Test Option C: $(0, 1, 1, 0, 0)$

Substitute: $0 + 1 + 0 = 1 + 2 (0) ⟹ 1 = 1$ .

This is mathematically valid. (This represents Pos + Neg = Neg, no overflow).

Step 5: Test Option D: $(0, 0, 1, 0, 0)$

Substitute: $0 + 0 + 0 = 1 + 2 (0) ⟹ 0 = 1$ .

This is a mathematical contradiction. It is physically impossible for the adder to produce a sum bit of 1 and a carry out of 0 when both operands and the carry in are 0.

Answer: D

Question 2 · Instruction Set, Datapath and Memory Organization MCQ

An Instruction Set Architecture (ISA) specification explicitly defines the following hardware-software contract:

The processor provides exactly $32$ general-purpose registers, each $32$ bits wide.
All arithmetic and logical instructions must specify exactly three register operands (two sources, one destination).
Load and Store instructions specify exactly one register operand and one $16 -bit$ signed immediate offset.
The Program Counter (PC) is maintained by the hardware and is not accessible as a general-purpose register.

Based strictly on this ISA contract, which of the following is IMPOSSIBLE to support or execute?

A.
An instruction that computes the sum of R1 and R2, and writes the result to R3.
B.
An instruction that loads a 32-bit word from the memory address (R4 + 200) into R5.
C.
An instruction that adds a 16-bit immediate value directly to R1 and writes the result to R2.
D.
A microarchitectural design that uses the same physical ALU hardware to calculate effective addresses for Load instructions and to perform register-to-register addition.

Correct Answer:

Step-by-Step Solution

Key idea: The ISA defines the strict boundary of what software can request. Any instruction format that violates the explicit operand rules of the contract is impossible to encode or execute.

Step 1: Evaluate Option A. "Sum of R1 and R2, writes to R3". This uses exactly three register operands. This perfectly matches Rule 2. (Possible).

Step 2: Evaluate Option B. "Load from (R4 + 200) into R5". This uses one register (R4) and one 16-bit immediate (200). This perfectly matches Rule 3. (Possible).

Step 3: Evaluate Option C. "Adds 16-bit immediate to R1, writes to R2". This uses two registers and one immediate. This violates Rule 2, which strictly requires THREE register operands for all arithmetic instructions. (IMPOSSIBLE).

Step 4: Evaluate Option D. "Same physical ALU for address calculation and arithmetic". This describes the microarchitecture (hardware implementation), not the ISA. The ISA does not restrict hardware reuse. (Possible).

Answer: C

Question 3 · Processor Performance, Pipelining and Hazards MCQ

A non-pipelined processor P1 has a CPI of 5 and operates at 1 GHz. It is redesigned into a 5-stage pipelined processor P2 operating at 2 GHz. For a specific program, the instruction mix is 50% ALU (0 stall cycles), 30% Load (2 stall cycles), and 20% Branch (1 stall cycle). Based on this information, which ONE of the following observations is CORRECT?

A.
The speedup of P2 over P1 is exactly 5, which is equal to the number of pipeline stages.
B.
The speedup of P2 over P1 is greater than the ratio of their clock frequencies.
C.
If the branch stall penalty is doubled, the speedup of P2 over P1 will fall below 4.0.
D.
The actual CPI of P2 is 1.8, making its execution time exactly 2.5 times faster than P1.

Correct Answer:

Step-by-Step Solution

Insight: This is a performance observation question requiring you to calculate the actual CPI and execution time for both processors, then compare the speedup against theoretical bounds and alternative scenarios.

Exam route: Calculate execution time per instruction for P1 and P2. Compute actual speedup. Evaluate each statement based on these values.

Learning route:

Step 1: P1 execution time per instruction = $CPI \times T_{cy c l e} = 5 \times \frac{1}{1 GHz} = 5 ns$ .

Step 2: P2 actual CPI = $1 + (0.30 \times 2) + (0.20 \times 1) = 1 + 0.6 + 0.2 = 1.8$ .

Step 3: P2 execution time per instruction = $1.8 \times \frac{1}{2 GHz} = 0.9 ns$ .

Step 4: Speedup of P2 over P1 = $\frac{5}{0.9} \approx 5.55$ .

Step 5: Evaluate Option A: Speedup is 5.55, not 5. (False)

Step 6: Evaluate Option B: Ratio of clock frequencies = $\frac{2 GHz}{1 GHz} = 2$ . Since $5.55 > 2$ , this statement is True.

Step 7: Evaluate Option C: If branch penalty is 2, P2 CPI = $1 + (0.30 \times 2) + (0.20 \times 2) = 2.0$ . P2 time = $2.0 \times 0.5 = 1.0 ns$ . Speedup = $\frac{5}{1.0} = 5.0$ . This is not below 4.0. (False)

Step 8: Evaluate Option D: Execution time ratio is 5.55, not 2.5. (False)

Answer: B

Question 4 · Cache Memory, Memory Hierarchy and Address Translation NAT

A system uses a VIPT (Virtual Index, Physical Tag) cache with a page size of $4$ KB and a cache block size of $32$ bytes. The maximum number of sets the cache can have, such that the synonyms problem is guaranteed not to occur, is ________.

Correct Answer:

128.00

Step-by-Step Solution

Key idea: In a VIPT cache, synonyms are avoided when the index bits are a subset of the page offset bits. This gives the constraint $sets \times block_size \leq page_size$ .

Step 1: Identify the given parameters.

Page size $= 4 KB = 4096$ bytes.

Block size $= 32$ bytes.

Step 2: Apply the VIPT constraint.

$sets \leq page_size / block_size$

$sets \leq 4096/32 = 128$ .

Step 3: Verify the boundary.

At $128$ sets: index bits $= lo g_{2} (128) = 7$ .

Page offset bits $= lo g_{2} (4096) = 12$ .

Block offset bits $= lo g_{2} (32) = 5$ .

Available for index $= 12 - 5 = 7$ bits.

Since $7 \leq 7$ , the constraint is satisfied.

Answer: 128.00

Question 5 · Input-Output, Interrupts and DMA MCQ

A processor uses a vectored interrupt mechanism. The interrupt vector table is stored in a dedicated memory region of $256$ bytes. Each entry in the table is a $32$ -bit address pointing to the corresponding Interrupt Service Routine (ISR). The hardware interrupt controller uses a priority encoder that generates a $5$ -bit interrupt identifier to index into this table. What is the MAXIMUM number of distinct interrupt sources that can be uniquely vectored to their ISRs without requiring any software polling to resolve the source?

A.
64
B.
128
C.
256
D.
32

Correct Answer:

Step-by-Step Solution

Key idea: This is a contradiction question testing the boundary constraints of a vectored interrupt system. The maximum number of sources is limited by the most restrictive hardware or memory constraint.

Step 1: Calculate the maximum number of entries the memory table can hold.

Table size = $256$ bytes. Each entry = $32$ bits = $4$ bytes.

Table capacity = $256/4 = 64$ entries.

Step 2: Calculate the maximum number of unique indices the hardware can generate.

Hardware identifier = $5$ bits.

Hardware capacity = $2^{5} = 32$ unique indices.

Step 3: Determine the binding constraint. The system can only support as many vectored sources as the hardware can uniquely identify, provided the table is large enough.

Maximum sources = $min (64, 32) = 32$ .

Answer: 32

Question 6 · Secondary Storage and Disk Performance MSQ

Consider a disk pack with 5 platters. The top and bottom surfaces are reserved for protection. The total capacity of the disk is exactly $10 TB$ ( $10 \times 2^{40}$ bytes). The number of sectors per track is a power of 2 and lies strictly between 1000 and 2000. Each sector holds 512 bytes.

Which of the following statements are true?

I. The number of sectors per track is uniquely determined to be 1024.

II. The number of cylinders is 2097152.

III. The number of cylinders is 2621440.

IV. The total number of tracks on the disk is 20971520.

A.
I, II, III
B.
I, III, IV
C.
II, III, IV
D.
I, II, III, IV

Correct Answer:

["B"]

Step-by-Step Solution

Key idea: This is a bounding and constraint-satisfaction problem. The total capacity formula $C = \frac{Total Bytes}{S \times T _{s} \times B}$ must yield an integer, which restricts the possible values of $T_{s}$ .

Step 1: Determine usable surfaces ( $S$ ).

The disk has 5 platters, but the top and bottom surfaces are reserved.

$S = 2 \times 5 - 2 = 8$ surfaces.

Step 2: Bound the sectors per track ( $T_{s}$ ).

Total Capacity = $10 \times 2^{40}$ bytes.

Bytes per sector ( $B$ ) = 512 = $2^{9}$ .

Capacity per cylinder = $S \times T_{s} \times B = 8 \times T_{s} \times 2^{9} = 2^{12} \times T_{s}$ .

Number of cylinders = $\frac{10 \times 2 ^{40}}{2 ^{12} \times T _{s}} = \frac{10 \times 2 ^{28}}{T _{s}}$ .

For the number of cylinders to be an integer, $T_{s}$ must divide $10 \times 2^{28}$ .

We are given $T_{s}$ is a power of 2 and $1000 < T_{s} < 2000$ . The only power of 2 in this range is $1024 = 2^{10}$ .

Thus, Statement I is True.

Step 3: Calculate cylinders and tracks.

With $T_{s} = 1024 = 2^{10}$ :

Number of cylinders = $\frac{10 \times 2 ^{28}}{2 ^{10}} = 10 \times 2^{18} = 10 \times 262144 = 2621440$ .

Thus, Statement III is True, and Statement II is False.

Total number of tracks = $S \times Cylinders = 8 \times 2621440 = 20971520$ .

Thus, Statement IV is True.

Note: If you incorrectly ignored the reserved surfaces and used $S = 10$ , you would get Cylinders = 2097152 (Statement II), but the Total Tracks would still be $10 \times 2097152 = 20971520$ . Total tracks are invariant to the number of surfaces because $Total Tracks = \frac{Total Capacity}{T _{s} \times B}$ .

Answer: I, III, IV are true.

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Computer Organization and Architecture Practice Questions for GATE CS

About Computer Organization and Architecture Practice Questions

Computer Organization and Architecture Weightage in GATE CS

Computer Organization and Architecture Chapter Matrix

More from Computer Organization and Architecture

One Solved Question from Each Computer Organization and Architecture Chapter

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