Input-Output, Interrupts and DMA Practice Questions for GATE CS

Solve 121+ Input-Output, Interrupts and DMA practice questions for GATE CS with answers and detailed solutions. Free sample questions below.

Chapter Roadmap: Input-Output, Interrupts and DMA

Chapter Roadmap

Input-Output, Interrupts and DMA

1. Interrupt Processing and Priority

Hardware signals, ISR sequence, vectored vs non-vectored, daisy chaining.

Weightage: Moderate

2. DMA Modes, Throughput and Bulk Transfer

Cycle stealing, burst mode, data transfer rate calculations.

Weightage: High

3. Polling and I/O Processing Overhead

Programmed I/O, CPU cycle consumption, overhead analysis.

Weightage: Low

Goal: Master how the CPU efficiently manages external devices without wasting cycles, transitioning from software polling to hardware-driven interrupts and DMA.

Interrupt Processing and Priority Mechanisms

Input-Output, Interrupts and DMA

Interrupt Processing and Priority Mechanisms

The foundation of how a CPU reacts to external events efficiently.

What you will learn here:

The exact sequence of steps the processor takes when an interrupt arrives.
The critical difference between vectored and non-vectored interrupts.
How daisy-chaining resolves priority conflicts in hardware.
Common traps in calculating interrupt overhead and context switching.

Input-Output, Interrupts and DMA: Solved Questions with Step-by-Step Explanations (10 Problems)

Question 1 · Computer Organization and Architecture MCQ

During the interrupt handling cycle, immediately after the CPU finishes the currently executing instruction, what is the next critical hardware action performed?

A.
The CPU disables the cache memory to prevent data corruption.
B.
The CPU clears the instruction pipeline and fetches the first instruction of the ISR.
C.
The CPU saves the current Program Counter (PC) and Processor Status Word (PSW) to the stack or a dedicated register.
D.
The CPU sends an interrupt acknowledge (INTA) signal to all connected devices.

Correct Answer:

Step-by-Step Solution

Key idea: This is a sequence question testing the exact hardware steps of the interrupt handling cycle.

Step 1: When an interrupt arrives, the CPU cannot abort the current instruction mid-execution without corrupting the system state. Thus, it must first finish the current instruction.

Step 2: Before the CPU can jump to the Interrupt Service Routine (ISR), it must remember where it was in the main program so it can return later.

Step 3: To do this, the hardware automatically saves the Program Counter (PC), which holds the return address, and the Processor Status Word (PSW), which holds the condition codes and interrupt enable flags.

Step 4: Only after the context is safely saved does the CPU load the PC with the ISR address.

Answer: C

Question 2 · Computer Organization and Architecture MCQ

In a non-vectored interrupt mechanism, how does the CPU identify which device generated the interrupt?

A.
The device places its unique ISR address on the data bus.
B.
The CPU executes a software polling routine to check device status flags.
C.
The interrupt controller sends a hardware daisy-chain acknowledge signal.
D.
The device asserts a unique binary code on the address bus.

Correct Answer:

Step-by-Step Solution

Key idea: This is a definition question testing the difference between vectored and non-vectored interrupts.

Step 1: In a vectored interrupt, the interrupting hardware directly provides the memory address of its Interrupt Service Routine (ISR) on the system bus.

Step 2: In a non-vectored interrupt, the hardware only signals that an interrupt occurred, but does not provide the address or the source identity.

Step 3: Therefore, the CPU must jump to a generic interrupt handler and execute a software routine (often polling device status registers) to identify exactly which device requested the service.

Answer: B

Question 3 · Computer Organization and Architecture MCQ

A DMA controller transfers $w$ bytes per DMA cycle. If the processor clock frequency is $f$ Hz and the fraction of CPU cycles used for DMA is $p$ , which expression gives the data transfer rate in bytes per second?

A.
$8 \cdot w \cdot p \cdot f$
B.
$w \cdot p \cdot f$
C.
$w \cdot f / p$
D.
$8 \cdot w \cdot f$

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct formula application question, recognizable because it provides the variables $f$ , $p$ , and $w$ and asks for the data transfer rate.

Step 1: The processor clock frequency $f$ gives the total number of CPU cycles per second.

Step 2: The fraction of CPU cycles used for DMA is $p$ . Therefore, the number of DMA cycles per second is $p \cdot f$ .

Step 3: The DMA controller transfers $w$ bytes per DMA cycle.

Step 4: To find the total bytes transferred per second, multiply the bytes per cycle by the number of DMA cycles per second: $w \cdot (p \cdot f) = w \cdot p \cdot f$ .

Step 5: The question specifically asks for the rate in bytes per second, so no conversion to bits is needed.

Answer: B

Question 4 · Computer Organization and Architecture MCQ

In a hardware daisy-chain interrupt priority mechanism, the interrupt acknowledge (INTA) signal is passed serially from one device to the next. Which device effectively receives the highest priority?

A.
The device that generates interrupts most frequently.
B.
The device located at the end of the daisy chain.
C.
The device with the highest data transfer rate.
D.
The device positioned closest to the CPU, which receives the INTA signal first.

Correct Answer:

Step-by-Step Solution

Key idea: This is a conceptual question testing how hardware priority is resolved in a daisy-chain configuration.

Step 1: In a daisy chain, all devices share a single interrupt request line to the CPU. When the CPU acknowledges the interrupt, it sends an Interrupt Acknowledge (INTA) signal.

Step 2: This INTA signal is passed serially from the CPU to Device 1, then to Device 2, and so on.

Step 3: The first device in the chain that actually requested an interrupt will "block" the INTA signal from propagating further down the chain and will place its vector address on the bus.

Step 4: Therefore, the device physically closest to the CPU (first in the chain) has the highest priority, as it gets the first opportunity to claim the acknowledge signal.

Answer: D

Question 5 · Computer Organization and Architecture MCQ

What is the primary advantage of using an interrupt-driven I/O mechanism over programmed I/O (polling)?

A.
The CPU does not waste cycles continuously checking the device status.
B.
The CPU can execute I/O instructions faster than memory instructions.
C.
The device can directly write to the CPU registers without bus arbitration.
D.
The system bus bandwidth is increased for all connected peripherals.

Correct Answer:

Step-by-Step Solution

Key idea: This is a conceptual comparison question testing the fundamental purpose of interrupts versus polling.

Step 1: In programmed I/O (polling), the CPU must constantly execute a loop to check the status register of the I/O device to see if it is ready. This wastes millions of CPU cycles if the device is slow.

Step 2: In an interrupt-driven mechanism, the CPU executes other useful tasks and only pauses its current flow when the I/O device sends a hardware signal (interrupt) indicating it needs attention.

Step 3: Therefore, the primary advantage is the elimination of constant, wasteful status checking.

Answer: A

Question 6 · Computer Organization and Architecture MCQ

During the interrupt handling cycle, why does the CPU typically disable further maskable interrupts immediately after saving the context?

A.
To prevent nested interrupts from corrupting the stack during the context switch
B.
To free up the data bus for the vector address
C.
To signal the device that the interrupt has been acknowledged
D.
To prevent the current instruction from being executed again

Correct Answer:

Step-by-Step Solution

Key idea: This is a conceptual question about the interrupt handling cycle, recognizable because it asks for the rationale behind a specific hardware action (disabling interrupts).

Step 1: When an interrupt occurs, the CPU saves the PC and PSW to the stack.

Step 2: The stack is a critical data structure used for context switching and subroutine calls.

Step 3: If another maskable interrupt were allowed to occur immediately, its handler would also try to push data onto the stack.

Step 4: This could lead to a corrupted stack state if the first context switch is not fully complete. Therefore, interrupts are disabled to protect the stack during this delicate phase.

Answer: A

Question 7 · Computer Organization and Architecture MCQ

A DMA controller uses 2% of the CPU cycles to transfer data. If the processor operates at a clock frequency of 5 MHz and transfers 4 bytes per DMA cycle, what is the data transfer rate in bytes per second?

A.
400,000
B.
200,000
C.
100,000
D.
50,000

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct formula application question, recognizable because it gives the clock frequency, cycle fraction, and bytes per cycle.

Step 1: Identify the given values: clock frequency $f = 5 MHz = 5 \times 1 0^{6} Hz$ , fraction of cycles $p = 2% = 0.02$ , and bytes per cycle $w = 4$ .

Step 2: Calculate the number of DMA cycles per second: $p \cdot f = 0.02 \times 5 \times 1 0^{6} = 100, 000 cycles/second$ .

Step 3: Calculate the data transfer rate in bytes per second by multiplying the bytes per cycle by the DMA cycles per second: $w \cdot (p \cdot f) = 4 \times 100, 000 = 400, 000 bytes/second$ .

Step 4: The question asks for the rate in bytes per second, so no further conversion is needed.

Answer: A

Question 8 · Computer Organization and Architecture MCQ

A DMA controller transfers 4 bytes per cycle. If the processor clock is 10 MHz and 2% of the CPU cycles are used for DMA, what is the data transfer rate in bytes per second?

A.
80,000
B.
800,000
C.
200,000
D.
4,000,000

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct formula application question, recognizable because it gives the clock frequency, cycle fraction, and bytes per cycle.

Step 1: Identify the given values: clock frequency $f = 10 MHz = 1 0^{7} Hz$ , fraction of cycles $p = 2% = 0.02$ , and bytes per cycle $w = 4$ .

Step 2: Calculate the number of DMA cycles per second: $p \cdot f = 0.02 \times 1 0^{7} = 200, 000 cycles/second$ .

Step 3: Calculate the data transfer rate in bytes per second by multiplying the bytes per cycle by the DMA cycles per second: $w \cdot (p \cdot f) = 4 \times 200, 000 = 800, 000 bytes/second$ .

Step 4: The question asks for the rate in bytes per second, so no further conversion to bits is needed.

Answer: B

Question 9 · Computer Organization and Architecture MCQ

When solving a DMA throughput numerical, what is the essential relationship needed to find the fraction of CPU cycles used by DMA?

A.
The total number of instructions in the ISR.
B.
The physical distance between the device and memory.
C.
The number of CPU cycles required to transfer one unit of data.
D.
The voltage level of the interrupt request signal.

Correct Answer:

Step-by-Step Solution

Key idea: This is a methodology question about DMA numericals, recognizable because it asks for the essential relationship needed to solve throughput problems.

Step 1: In DMA numericals, you are often given the device transfer rate and the processor frequency, and asked to find the CPU cycle fraction (or vice versa).

Step 2: To bridge the gap between device rate (e.g., characters per second) and CPU cycles, you must know how many CPU cycles are consumed to transfer one character (or word).

Step 3: Once you have the cycles per character, you can multiply by the device rate to find the total DMA cycles per second, and then divide by the total CPU cycles per second to find the fraction.

Answer: C

Question 10 · Computer Organization and Architecture MCQ

When tracing interrupt execution, what is the correct chronological order of the first three hardware actions after an interrupt request is recognized?

A.
Save PC -> Finish instruction -> Disable interrupts
B.
Finish instruction -> Save PC -> Disable interrupts
C.
Disable interrupts -> Save PC -> Finish instruction
D.
Finish instruction -> Disable interrupts -> Save PC

Correct Answer:

Step-by-Step Solution

Key idea: This is a sequence tracing question, recognizable because it asks for the exact chronological order of the hardware interrupt handling cycle.

Step 1: The CPU cannot safely pause an instruction mid-execution. Therefore, the very first action is to finish the currently executing instruction.

Step 2: Once the instruction is complete, the CPU must preserve the return address and state. It does this by saving the Program Counter (PC) and Processor Status Word (PSW) to the stack.

Step 3: Before jumping to the ISR and potentially corrupting the stack with nested interrupts, the hardware disables further maskable interrupts.

Step 4: The correct sequence is: Finish instruction -> Save PC -> Disable interrupts.

Answer: B

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Input-Output, Interrupts and DMA Practice Questions for GATE CS

Chapter Roadmap: Input-Output, Interrupts and DMA

Chapter Roadmap

Interrupt Processing and Priority Mechanisms

Interrupt Processing and Priority Mechanisms

Input-Output, Interrupts and DMA: Solved Questions with Step-by-Step Explanations (10 Problems)

Step-by-Step Solution

Step-by-Step Solution

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