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Computer Organization and Architecture Practice Questions for GATE CS

GATE CS Computer Organization and Architecture: 1 units and 6 chapters, weightage from 66 previous year questions across 10 papers, a study order by exam weig

A question from this chapter

Question 1

Level 1: Warm-up

What is the maximum positive integer that can be represented in a 12-bit 2's complement system?

Question 2

Level 1: Warm-up

Consider the following Assertion (A) and Reason (R) regarding array translation in a generic load-store assembly language without auto-scaling addressing modes: Assertion (A): To access the i -th element of an array of 16-bit integers, the index i must be multiplied by 2 before adding to the base address. Reason (R): The memory is byte-addressable, meaning each address points to an 8-bit unit, so a 16-bit element spans 2 addressable units. Which of the following is correct?

Question 3

Level 1: Warm-up

Statement 1: The theoretical maximum speedup of a k -stage pipeline is bounded by k, assuming ideal conditions with no stalls. Statement 2: When calculating the actual speedup of a pipelined processor, the increase in clock cycle time due to latch overhead can be ignored if the number of pipeline stages is sufficiently large. Which of the following is correct?

Question 4

Level 1: Warm-up

A processor uses 32-bit addresses and has a 128 KB, 8-way set-associative cache. The block size is not specified but is known to be a power of two. What is the number of bits in the tag field?

Question 5

Level 1: Warm-up

During the interrupt handling cycle, immediately after the CPU finishes the currently executing instruction, what is the next critical hardware action performed?

Question 6

Level 1: Warm-up

A disk has 8 surfaces, 500 cylinders, and 100 sectors per track. Each sector holds 512 bytes. What is the minimum number of bytes required to store data on exactly one full cylinder of this disk?

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Computer Organization and Architecture Practice Questions for GATE CS

GATE CS Computer Organization and Architecture: 1 units and 6 chapters, weightage from 66 previous year questions across 10 papers, a study order by exam weight and 1032 practice questions.

About Computer Organization and Architecture Practice Questions

1032 practice questions for Computer Organization and Architecture in GATE CS, sorted chapter by chapter and graded from basic to exam level, each with a full solution.

GATE CS Computer Organization and Architecture Unit-wise Weightage from Past Papers

We counted every GATE CS Computer Organization and Architecture previous year question in our bank (66 questions from 10 papers) and grouped them by unit.

Unit	Chapters	PYQs	Share of section	Avg per paper
Computer Organization and Architecture	6	66	100%	6.6

Suggested Computer Organization and Architecture Study Order for GATE CS

Computer Organization and Architecture: 100% of past Computer Organization and Architecture questions, about 6.6 per paper.

Start where the marks are. Units at the top of this list have appeared most often in past GATE CS papers.

Units in GATE CS Computer Organization and Architecture

Computer Organization and Architecture Practice Questions (6 chapters)

All Computer Organization and Architecture chapters

One Solved Question from Each Computer Organization and Architecture Chapter

Question 1 · Number Representation and Computer Arithmetic MCQ

What is the maximum positive integer that can be represented in a 12-bit 2's complement system?

A.
2048
B.
4095
C.
4096
D.
2047

Correct Answer:

Step-by-Step Solution

Key idea: In 2's complement, the range is asymmetric. The maximum positive value uses all bits except the sign bit.

Step 1: Recall the formula for the maximum positive value in $n$ -bit 2's complement.

Maximum positive value = $2^{n - 1} - 1$

Step 2: Substitute $n = 12$ .

Maximum positive value = $2^{12 - 1} - 1 = 2^{11} - 1$

Step 3: Calculate $2^{11}$ .

$2^{11} = 2048$

Step 4: Subtract 1.

$2048 - 1 = 2047$

Answer: $2047$ (Option D)

Question 2 · Instruction Set, Datapath and Memory Organization MCQ

Consider the following Assertion (A) and Reason (R) regarding array translation in a generic load-store assembly language without auto-scaling addressing modes:

Assertion (A): To access the $i$ -th element of an array of 16-bit integers, the index $i$ must be multiplied by 2 before adding to the base address.

Reason (R): The memory is byte-addressable, meaning each address points to an 8-bit unit, so a 16-bit element spans 2 addressable units.

Which of the following is correct?

A.
Both A and R are true, and R is the correct explanation of A.
B.
Both A and R are true, but R is NOT the correct explanation of A.
C.
A is true, but R is false.
D.
A is false, but R is true.

Correct Answer:

Step-by-Step Solution

Key idea: Effective address calculation requires scaling the element index by the element size in bytes.

Step 1: Evaluate Assertion (A). In a generic assembly without auto-scaling, the programmer must manually compute the byte offset. For 16-bit (2-byte) integers, the index $i$ must indeed be multiplied by 2. (A is True).

Step 2: Evaluate Reason (R). Modern main memory is byte-addressable. An 8-bit unit is 1 byte. A 16-bit integer occupies 2 bytes, hence it spans 2 addressable units. (R is True).

Step 3: Check the link. Does R explain A? Yes. The manual multiplication by 2 in A is required specifically <b>because</b> memory is byte-addressable and the element is 2 bytes wide (as stated in R).

Answer: Both A and R are true, and R is the correct explanation of A.

Question 3 · Processor Performance, Pipelining and Hazards MCQ

Statement 1: The theoretical maximum speedup of a $k$ -stage pipeline is bounded by $k$ , assuming ideal conditions with no stalls.

Statement 2: When calculating the actual speedup of a pipelined processor, the increase in clock cycle time due to latch overhead can be ignored if the number of pipeline stages is sufficiently large.

Which of the following is correct?

A.
Statement 1 only
B.
Statement 2 only
C.
Both statements
D.
Neither statement

Correct Answer:

Step-by-Step Solution

Key idea: This is a bounding question evaluating the fundamental constraints of pipeline speedup calculations.

Step 1: Evaluate Statement 1. In an ideal pipeline with no stalls and no clock rate change, the speedup is exactly $k$ . This is the theoretical upper bound. Statement 1 is true.

Step 2: Evaluate Statement 2. Latch overhead increases the clock cycle time, which directly reduces the clock rate and thus the actual speedup. This overhead is a physical constraint and can never be ignored in exact speedup calculations, regardless of the number of stages. Statement 2 is false.

Step 3: Conclude that only Statement 1 is true.

Answer: A

Question 4 · Cache Memory, Memory Hierarchy and Address Translation MCQ

A processor uses 32-bit addresses and has a 128 KB, 8-way set-associative cache. The block size is not specified but is known to be a power of two. What is the number of bits in the tag field?

A.
15
B.
16
C.
20
D.
18

Correct Answer:

Step-by-Step Solution

Key idea: When block size is not given, use the cancellation trick — block size terms cancel out in the calculation. The Cancellation Trick:

Tag = Address - lo g_{2} (Cache size) + lo g_{2} (K)

Step 1: Apply the formula. Tag =

32 - lo g_{2} (128 KB) + lo g_{2} (8)

Tag =

32 - lo g_{2} (2^{17}) + lo g_{2} (2^{3})

Tag =

32 - 17 + 3

Tag =

18

bits. Why this works: Index bits =

lo g_{2} (Sets) = lo g_{2} (\frac{Cache / B}{K}) = lo g_{2} (Cache) - lo g_{2} (B) - lo g_{2} (K)

Offset bits =

lo g_{2} (B)

Index + Offset =

lo g_{2} (Cache) - lo g_{2} (B) - lo g_{2} (K) + lo g_{2} (B) = lo g_{2} (Cache) - lo g_{2} (K)

Tag = Address - (Index + Offset) = Address -

lo g_{2} (Cache) + lo g_{2} (K)

Answer: 18 bits.

Question 5 · Input-Output, Interrupts and DMA MCQ

During the interrupt handling cycle, immediately after the CPU finishes the currently executing instruction, what is the next critical hardware action performed?

A.
The CPU disables the cache memory to prevent data corruption.
B.
The CPU clears the instruction pipeline and fetches the first instruction of the ISR.
C.
The CPU saves the current Program Counter (PC) and Processor Status Word (PSW) to the stack or a dedicated register.
D.
The CPU sends an interrupt acknowledge (INTA) signal to all connected devices.

Correct Answer:

Step-by-Step Solution

Key idea: This is a sequence question testing the exact hardware steps of the interrupt handling cycle.

Step 1: When an interrupt arrives, the CPU cannot abort the current instruction mid-execution without corrupting the system state. Thus, it must first finish the current instruction.

Step 2: Before the CPU can jump to the Interrupt Service Routine (ISR), it must remember where it was in the main program so it can return later.

Step 3: To do this, the hardware automatically saves the Program Counter (PC), which holds the return address, and the Processor Status Word (PSW), which holds the condition codes and interrupt enable flags.

Step 4: Only after the context is safely saved does the CPU load the PC with the ISR address.

Answer: C

Question 6 · Secondary Storage and Disk Performance MCQ

A disk has 8 surfaces, 500 cylinders, and 100 sectors per track. Each sector holds 512 bytes. What is the minimum number of bytes required to store data on exactly one full cylinder of this disk?

A.
409,600
B.
204,800,000
C.
819,200
D.
4,096,000

Correct Answer:

Step-by-Step Solution

Key idea: This is a contradiction question testing the Master Capacity Equation, specifically isolating the capacity of a single cylinder.

Step 1: Recall that a cylinder spans all surfaces. The capacity of one cylinder is the number of surfaces multiplied by the sectors per track multiplied by the bytes per sector.

Step 2: Identify the given values: $S = 8$ , $T_{s} = 100$ , $B = 512$ .

Step 3: Calculate the capacity of one cylinder: $8 \times 100 \times 512 = 409, 600$ bytes.

Step 4: Note that the 500 cylinders given in the problem is extra information for this specific question, as we only need the capacity of <i>one</i> cylinder.

Answer: 409,600.