Processor Performance, Pipelining and Hazards Practice Questions for GATE CS

Solve 200+ Processor Performance, Pipelining and Hazards practice questions for GATE CS with answers and detailed solutions. Free sample questions below.

Chapter Roadmap: Processor Performance, Pipelining and Hazards

Chapter Roadmap

Your journey through Processor Performance and Pipelining. Master these five stages to decode any pipeline question.

1. Pipeline Timing, Latency and Throughput

The foundation. How overlapping execution changes cycle time, total latency, and overall throughput.

Weightage: Foundational / Moderate

2. Pipeline CPI, Clock Rate and Stall Performance

Moving beyond ideal scenarios. Calculating the real Cycles Per Instruction when stalls occur.

Weightage: High

3. Data Dependencies, Hazards and Forwarding

Identifying Read-After-Write, Write-After-Read, and Write-After-Write hazards, and resolving them with data forwarding.

Weightage: High

4. Control Hazards and Branch Prediction

Handling jumps and branches. Static prediction, dynamic prediction, and branch target buffers.

Weightage: Moderate

5. Parallel Speedup and Multicore Performance

Amdahl's Law, Gustafson's Law, and the limits of scaling across multiple cores.

Weightage: Low to Moderate

Topic Hero: Pipeline Timing, Latency and Throughput

Pipeline Timing, Latency and Throughput

Overlapping execution to maximize instruction completion rate.

The Core Insight: Pipelining does not reduce the time it takes to execute a single instruction (latency). Instead, it increases the number of instructions completed per second (throughput) by overlapping their execution stages, much like an assembly line.

Latency Time for 1 instruction

Throughput Instructions per unit time

Processor Performance, Pipelining and Hazards: Solved Questions with Step-by-Step Explanations (10 Problems)

Question 1 · Computer Organization and Architecture MCQ

Statement 1: The theoretical maximum speedup of a $k$ -stage pipeline is bounded by $k$ , assuming ideal conditions with no stalls.

Statement 2: When calculating the actual speedup of a pipelined processor, the increase in clock cycle time due to latch overhead can be ignored if the number of pipeline stages is sufficiently large.

Which of the following is correct?

A.
Statement 1 only
B.
Statement 2 only
C.
Both statements
D.
Neither statement

Correct Answer:

Step-by-Step Solution

Key idea: This is a bounding question evaluating the fundamental constraints of pipeline speedup calculations.

Step 1: Evaluate Statement 1. In an ideal pipeline with no stalls and no clock rate change, the speedup is exactly $k$ . This is the theoretical upper bound. Statement 1 is true.

Step 2: Evaluate Statement 2. Latch overhead increases the clock cycle time, which directly reduces the clock rate and thus the actual speedup. This overhead is a physical constraint and can never be ignored in exact speedup calculations, regardless of the number of stages. Statement 2 is false.

Step 3: Conclude that only Statement 1 is true.

Answer: A

Question 2 · Computer Organization and Architecture MCQ

Which of the following statements regarding data forwarding (bypassing) in a standard 5-stage pipelined processor is strictly TRUE?

A.
Forwarding from the MEM/WB register to the EX stage completely eliminates the stall cycle for a LOAD instruction immediately followed by a dependent ALU instruction.
B.
EX to EX forwarding routes the result from the ALU output of the producer directly to the ALU input of the consumer, requiring 0 stall cycles for back-to-back ALU instructions.
C.
Data forwarding allows a consumer instruction to read the correct value directly from the register file before the producer has reached the Write Back stage.
D.
Forwarding hardware is primarily designed to resolve Write-After-Read (WAR) hazards that naturally occur in standard in-order pipelines.

Correct Answer:

Step-by-Step Solution

Key idea: This is a bounding question testing the exact capabilities and limitations of forwarding hardware.

Step 1: Evaluate Option A. A LOAD instruction only has its data ready at the end of the MEM stage. Even with MEM to EX forwarding, an immediately dependent ALU instruction needs the data at the beginning of its EX stage. This timing mismatch still requires exactly 1 stall cycle. (False).

Step 2: Evaluate Option B. For back-to-back ALU instructions, the producer generates the result at the end of its EX stage. EX to EX forwarding routes this directly to the consumer's ALU input for its EX stage. This requires 0 stall cycles. (True).

Step 3: Evaluate Option C. Forwarding bypasses the register file entirely; it does not read from the register file early. (False).

Step 4: Evaluate Option D. WAR hazards do not occur in standard in-order pipelines, and forwarding is designed for RAW hazards. (False).

Answer: Option B.

Question 3 · Computer Organization and Architecture MCQ

Assertion (A): In a standard 5-stage pipeline with full forwarding hardware, the instruction sequence ADD R1, R2, R3 followed immediately by SUB R4, R1, R5 requires zero stall cycles.

Reason (R): The result of the ADD instruction is available at the end of its Execute (EX) stage and can be forwarded directly from the EX/MEM pipeline register to the ALU input of the SUB instruction at the beginning of its EX stage.

A.
Both A and R are true, and R is the correct explanation of A.
B.
Both A and R are true, but R is NOT the correct explanation of A.
C.
A is true, but R is false.
D.
A is false, but R is true.

Correct Answer:

Step-by-Step Solution

Key idea: This is a construction question testing the precise hardware mechanism that resolves arithmetic hazards.

Step 1: Evaluate Assertion (A). An ALU instruction followed by a dependent ALU instruction is a classic arithmetic hazard. With full forwarding, this requires 0 stall cycles. Assertion A is true.

Step 2: Evaluate Reason (R). The ADD instruction produces its result at the end of the EX stage. This result is latched in the EX/MEM pipeline register. The SUB instruction needs this value at the beginning of its EX stage. The forwarding path routes the data directly from the EX/MEM register to the ALU input. Reason R is true and perfectly explains A.

Step 3: Conclude the relationship. Both are true, and R is the correct explanation.

Answer: Option A.

Question 4 · Computer Organization and Architecture MCQ

A 4-stage pipeline has individual stage delays of 10 ns, 15 ns, 12 ns, and 14 ns. The inter-stage pipeline registers (latches) have a delay of 2 ns each. What is the minimum clock cycle time (in ns) required for this pipeline to operate correctly without data corruption?

A.
15
B.
17
C.
53
D.
55

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct application of the pipeline cycle time formula, identifying the bottleneck stage.

Step 1: Recall the formula for the clock cycle time: $T_{cy c l e} = max (t_{1}, t_{2}, \dots, t_{k}) + t_{l a t c h}$ .

Step 2: Identify the maximum stage delay from the given values: $max (10, 15, 12, 14) = 15$ ns.

Step 3: Add the latch delay: $T_{cy c l e} = 15 + 2 = 17$ ns.

Answer: B

Question 5 · Computer Organization and Architecture NAT

A 4-stage pipeline has stage delays of 100, 120, 110, and 130 nanoseconds. The inter-stage registers have a delay of 10 nanoseconds. The total time to execute 50 independent instructions on this pipeline, assuming no stalls, is __________ nanoseconds.

Correct Answer:

7420.00

Step-by-Step Solution

Key idea: This is a direct formula application for total pipeline execution time.

Step 1: Identify the maximum stage delay, which is $max (100, 120, 110, 130) = 130$ ns.

Step 2: Calculate the clock cycle time: $T_{cy c l e} = max (t_{i}) + t_{l a t c h} = 130 + 10 = 140$ ns.

Step 3: Calculate the total number of cycles for $n = 50$ instructions in a $k = 4$ stage pipeline: $C y c l es = k + n - 1 = 4 + 50 - 1 = 53$ cycles.

Step 4: Compute the total execution time: $T_{t o t a l} = 53 \times 140 = 7420$ ns.

Answer: 7420.00

Question 6 · Computer Organization and Architecture MCQ

For a $k$ -stage pipeline, the speedup $S$ is bounded by a maximum theoretical value as the number of instructions $n$ approaches infinity. If a pipeline has 8 stages, what is this maximum boundary value for the speedup?

A.
8
B.
7
C.
9
D.
Infinity

Correct Answer:

Step-by-Step Solution

Key idea: This is an observation question about the asymptotic boundary of pipeline speedup.

Step 1: Recall the speedup formula: $S = \frac{T _{n o n - p i p e}}{T _{t o t a l}} = \frac{n \times k}{k + n - 1}$ .

Step 2: Observe the limit as $n \to \infty$ . The $- 1$ and $+ k$ become negligible compared to $n$ .

Step 3: The limit simplifies to $\frac{n \times k}{n} = k$ .

Step 4: For an 8-stage pipeline, $k = 8$ . The maximum boundary value is 8.

Answer: A

Question 7 · Computer Organization and Architecture MCQ

Statement 1: The clock cycle time of a pipeline is bounded below by the delay of the slowest pipeline stage.

Statement 2: The inter-stage latch delay can be ignored if the stage delays are significantly larger.

Which of the following is correct?

A.
Statement 1 only
B.
Statement 2 only
C.
Both statements
D.
Neither statement

Correct Answer:

Step-by-Step Solution

Key idea: This is a bounding question evaluating the fundamental constraints of pipeline cycle time calculation.

Step 1: Evaluate Statement 1. The clock cycle time is $T_{cy c l e} = max (t_{i}) + t_{l a t c h}$ . Since $t_{l a t c h} \geq 0$ , $T_{cy c l e} \geq max (t_{i})$ . Thus, it is bounded below by the slowest stage delay. Statement 1 is true.

Step 2: Evaluate Statement 2. The latch delay represents the setup and propagation time of the pipeline registers. It must always be added to the maximum stage delay. Ignoring it violates the timing constraint and leads to data corruption, regardless of how large the stage delays are. Statement 2 is false.

Step 3: Conclude that only Statement 1 is true.

Answer: A

Question 8 · Computer Organization and Architecture MCQ

A program executes 500 instructions on a pipeline where the ideal CPI is 1. Due to data hazards, the actual CPI is measured to be 1.2. How many total stall cycles are introduced during this execution compared to the ideal case?

A.
100
B.
400
C.
500
D.
600

Correct Answer:

Step-by-Step Solution

Key idea: This is a casework question calculating the absolute number of stall cycles from the CPI difference.

Step 1: Identify the given values: Instruction count ( $n$ ) = 500, Ideal CPI = 1, Actual CPI = 1.2.

Step 2: Calculate the ideal total cycles: $500 \times 1 = 500$ cycles.

Step 3: Calculate the actual total cycles: $500 \times 1.2 = 600$ cycles.

Step 4: Find the difference (total stall cycles): $600 - 500 = 100$ cycles.

Answer: A

Question 9 · Computer Organization and Architecture MCQ

An instruction mix consists of 50% ALU (0 stalls), 30% Load (2 stalls), and 20% Branch (1 stall). A student incorrectly calculates the average stall cycles per instruction by simply summing the stall penalties of all instruction types (0 + 2 + 1). What is the absolute difference between the student's incorrect calculation and the correct average stall cycles per instruction?

A.
0.8
B.
1.2
C.
2.2
D.
3.0

Correct Answer:

Step-by-Step Solution

Key idea: This is a contradiction question highlighting the error of unweighted summation versus the correct weighted average for stall cycles.

Step 1: Calculate the correct average stall cycles: $(0.5 \times 0) + (0.3 \times 2) + (0.2 \times 1) = 0 + 0.6 + 0.2 = 0.8$ .

Step 2: Identify the student's incorrect calculation: $0 + 2 + 1 = 3.0$ .

Step 3: Find the absolute difference: $∣3.0 - 0.8∣ = 2.2$ .

Answer: C

Question 10 · Computer Organization and Architecture MCQ

Assertion (A): The total execution time of a program on a pipelined processor is calculated as the product of the instruction count, the actual CPI, and the clock cycle time.

Reason (R): The actual CPI is a dimensionless quantity representing the average number of clock cycles per instruction, and multiplying it by the instruction count directly yields the total execution time in seconds.

A.
Both A and R are true and R is the correct explanation of A.
B.
Both A and R are true but R is NOT the correct explanation of A.
C.
A is true but R is false.
D.
A is false but R is true.

Correct Answer:

Step-by-Step Solution

Key idea: This is a construction and unit analysis question evaluating the assertion-reason pair for pipeline execution time.

Step 1: Evaluate Assertion (A). The formula $T_{e x ec} = Instruction Count \times Actual CPI \times T_{cy c l e}$ correctly constructs the total execution time. This is true.

Step 2: Evaluate Reason (R). The actual CPI is indeed dimensionless (cycles/instruction). Multiplying it by the instruction count yields the total number of clock cycles (dimension: cycles). However, to get time in seconds, you must multiply by the clock cycle time (seconds/cycle). Reason (R) claims this product directly yields seconds, which is a unit mismatch. Thus, Reason (R) is false.

Step 3: Conclude that A is true, but R is false.

Answer: C

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Processor Performance, Pipelining and Hazards Practice Questions for GATE CS

Chapter Roadmap: Processor Performance, Pipelining and Hazards

Chapter Roadmap

1. Pipeline Timing, Latency and Throughput

2. Pipeline CPI, Clock Rate and Stall Performance

3. Data Dependencies, Hazards and Forwarding

4. Control Hazards and Branch Prediction

5. Parallel Speedup and Multicore Performance

Topic Hero: Pipeline Timing, Latency and Throughput

Pipeline Timing, Latency and Throughput

Processor Performance, Pipelining and Hazards: Solved Questions with Step-by-Step Explanations (10 Problems)

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