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Digital Logic Notes for GATE CS

GATE CS Digital Logic: 1 units and 4 chapters, weightage from 33 previous year questions across 10 papers, a study order by exam weight and 537 practice quest

A question from this chapter

Question 1

Level 1: Warm-up

Assertion (A): In a 4-bit 2's complement system, adding (- 1) and (- 2) does not result in an overflow. Reason (R): The addition produces a carry out of 1 from the most significant bit, which indicates an overflow in signed arithmetic.

Question 2

Level 1: Warm-up

Assertion (A): For a 3-variable function F (A, B, C), if the sum-of-minterms is \sum m (1, 3, 4, 6), then the product-of-maxterms is \prod M (0, 2, 5, 7) . Reason (R): The arithmetic sum of the minterm indices and the maxterm indices equals the total number of rows in the truth table, which is 2^{3} = 8 .

Question 3

Level 1: Warm-up

Assertion (A): When implementing the function f (x, y, z) = \sum m (0, 1, 3, 4, 5, 6) using a 4-to-1 multiplexer with y and z as select lines, the data input I_{2} is connected to the variable x . Reason (R): Minterm 2 (binary 010) is absent from the function, and minterm 6 (binary 110) is present, so the transition from 0 to 1 in the implementation table requires the MSB variable x . Which of the following is correct?

Question 4

Level 1: Warm-up

An SR flip-flop has two inputs S and R . One specific input combination is invalid (undefined output). What is the number of valid input combinations for the SR flip-flop?

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Digital Logic Notes for GATE CS

GATE CS Digital Logic: 1 units and 4 chapters, weightage from 33 previous year questions across 10 papers, a study order by exam weight and 537 practice questions.

About Digital Logic Notes

Full study notes for Digital Logic in GATE CS, organised across 4 chapters. Each chapter page explains concepts from the basics with worked examples and the formulas you need.

GATE CS Digital Logic Unit-wise Weightage from Past Papers

We counted every GATE CS Digital Logic previous year question in our bank (33 questions from 10 papers) and grouped them by unit.

Unit	Chapters	PYQs	Share of section	Avg per paper
Digital Logic	4	33	100%	3.3

Suggested Digital Logic Study Order for GATE CS

Digital Logic: 100% of past Digital Logic questions, about 3.3 per paper.

Start where the marks are. Units at the top of this list have appeared most often in past GATE CS papers.

Units in GATE CS Digital Logic

Digital Logic Notes (4 chapters)

All Digital Logic chapters

One Solved Question from Each Digital Logic Chapter

Question 1 · Number Systems, Binary Arithmetic and Data Representation MCQ

Assertion (A): In a 4-bit 2's complement system, adding $(- 1)$ and $(- 2)$ does not result in an overflow.

Reason (R): The addition produces a carry out of 1 from the most significant bit, which indicates an overflow in signed arithmetic.

A.
Both A and R are true, and R is the correct explanation of A.
B.
Both A and R are true, but R is NOT the correct explanation of A.
C.
A is true, but R is false.
D.
A is false, but R is true.

Correct Answer:

Step-by-Step Solution

Key idea: This is a construction question testing the precise definition of overflow and the common trap of confusing carry-out with overflow.

Step 1: Evaluate Assertion (A). $(- 1)_{10} = 111 1_{2}$ , $(- 2)_{10} = 111 0_{2}$ .

Step 2: Add them: $1111 + 1110 = 11101$ . Discard the carry out. The 4-bit result is $110 1_{2}$ , which is $(- 3)_{10}$ .

Step 3: Since $- 3$ is within the 4-bit range $[- 8, 7]$ , no overflow occurred. Assertion (A) is TRUE.

Step 4: Evaluate Reason (R). The addition does produce a carry out of 1. However, in signed 2's complement arithmetic, a carry out does NOT indicate overflow. Overflow is determined by the sign bits or XOR of carries. Thus, Reason (R) is FALSE.

Answer: A is true, but R is false.

Question 2 · Boolean Algebra, Canonical Forms and Logic Minimization MCQ

Assertion (A): For a 3-variable function $F (A, B, C)$ , if the sum-of-minterms is $\sum m (1, 3, 4, 6)$ , then the product-of-maxterms is $\prod M (0, 2, 5, 7)$ .

Reason (R): The arithmetic sum of the minterm indices and the maxterm indices equals the total number of rows in the truth table, which is $2^{3} = 8$ .

A.
Both A and R are true and R is the correct explanation of A.
B.
A is true but R is false.
C.
Both A and R are true but R is not the correct explanation of A.
D.
A is false but R is true.

Correct Answer:

Step-by-Step Solution

Key idea: Verify the mathematical truth of the Assertion, then check the Reason for conceptual and arithmetic accuracy.

Step 1: Evaluate Assertion (A). For a 3-variable function, there are $2^{3} = 8$ total rows (0 to 7). The minterm indices are ${1, 3, 4, 6}$ . The maxterm indices must be the complement set: ${0, 1, 2, 3, 4, 5, 6, 7} ∖ {1, 3, 4, 6} = {0, 2, 5, 7}$ . Assertion (A) is TRUE.

Step 2: Evaluate Reason (R). The reason claims the "arithmetic sum" of the indices equals 8. Let's calculate the arithmetic sum: $(1 + 3 + 4 + 6) + (0 + 2 + 5 + 7) = 14 + 14 = 28$ .

Step 3: The arithmetic sum is 28, not 8. The correct concept is that the <i>union of the sets</i> of indices contains exactly 8 elements. Reason (R) is FALSE due to a unit mismatch (confusing set union size with arithmetic sum).

Answer: B

Question 3 · Combinational Logic Circuits and Data Selectors MCQ

Assertion (A): When implementing the function $f (x, y, z) = \sum m (0, 1, 3, 4, 5, 6)$ using a 4-to-1 multiplexer with $y$ and $z$ as select lines, the data input $I_{2}$ is connected to the variable $x$ .

Reason (R): Minterm 2 (binary 010) is absent from the function, and minterm 6 (binary 110) is present, so the transition from 0 to 1 in the implementation table requires the MSB variable $x$ .

Which of the following is correct?

A.
Both A and R are true and R is the correct explanation of A
B.
Both A and R are true but R is NOT the correct explanation of A
C.
A is true but R is false
D.
A is false but R is true

Correct Answer:

Step-by-Step Solution

Key idea: This is a construction problem testing the implementation table method with assertion-reason format.

Step 1: Verify Assertion (A):

Select lines: $S_{1} = y$ , $S_{0} = z$
For $I_{2}$ : $S_{1} S_{0} = 10$ (binary 2)
This corresponds to minterms where $y z = 10$ : minterm 2 (010) and minterm 6 (110)
Minterm 2 is absent (0), minterm 6 is present (1)
Implementation table: top=0, bottom=1 $\to$ input = MSB = $x$
Assertion A is True ✓

Step 2: Verify Reason (R):

Minterm 2 (010) is absent ✓
Minterm 6 (110) is present ✓
Transition 0→1 requires MSB variable $x$ ✓
Reason R is True ✓

Step 3: Check if R explains A:

Yes, the absence of minterm 2 and presence of minterm 6 directly leads to $I_{2} = x$

Answer: Both A and R are true, and R is the correct explanation of A (Option A)

Question 4 · Flip-Flops, Counters and Finite State Machines MCQ

An SR flip-flop has two inputs $S$ and $R$ . One specific input combination is invalid (undefined output). What is the number of valid input combinations for the SR flip-flop?

A.
2
B.
3
C.
4
D.
5

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct recall of the SR flip-flop characteristic table.

Step 1: An SR flip-flop has two binary inputs, $S$ and $R$ . The total number of input combinations is $2^{2} = 4$ : namely $(0, 0), (0, 1), (1, 0), (1, 1)$ .

Step 2: From the characteristic table:

$S = 0, R = 0$ : Hold (valid)
$S = 0, R = 1$ : Reset (valid)
$S = 1, R = 0$ : Set (valid)
$S = 1, R = 1$ : Undefined / Invalid

Step 3: Excluding the one invalid combination $(1, 1)$ , the number of valid combinations is $4 - 1 = 3$ .

Answer: B