Instruction Set Architecture (ISA)

Overview

The Instruction Set Architecture (ISA) represents the fundamental interface between a computer's software and its hardware. It defines the set of all commands, or machine instructions, that a processor can understand and execute. As such, the ISA provides an abstract model of the computer, specifying what the processor is capable of doing, without detailing how it accomplishes these tasks. A comprehensive grasp of the ISA is therefore indispensable for understanding how high-level programming constructs are translated into a language the machine can act upon, forming the bedrock of computer organization.

For the GATE examination, a mastery of ISA concepts is not merely academic but a practical necessity. Questions frequently probe the nuances of instruction formats, the efficiency of different addressing schemes, and the calculation of program execution metrics. This chapter is designed to build a robust conceptual framework for these topics. We will systematically dissect the components of machine instructions and explore the various methods by which operands are specified. This knowledge is critical for analyzing processor performance, understanding memory hierarchy interaction, and solving a wide array of problems presented in the exam.

We begin by examining the structure and classification of machine instructions themselves, from the opcode that specifies the operation to the operands that provide the data. Subsequently, we shall delve into the crucial topic of addressing modes, which dictate how the processor locates the data required for an instruction. By understanding these two pillars of the ISA, one gains the ability to reason about the design trade-offs inherent in any computer architecture and to predict the behavior of programs at the machine level.

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Chapter Contents

| # | Topic | What You'll Learn |
|---|-------|-------------------|
| 1 | Machine Instructions | Structure, types, and formats of instructions. |
| 2 | Addressing Modes | Techniques to calculate effective memory addresses. |

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Learning Objectives

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We now turn our attention to Machine Instructions...

Part 1: Machine Instructions

Introduction

The instruction, in its most fundamental form, is the primitive unit of command understood by a central processing unit (CPU). It is a collection of bits that directs the processor to perform a single, elementary operation. The complete collection of all such instructions that a specific CPU can execute is known as its instruction set. This set forms the vocabulary of the machine, providing the essential interface between the software that is written by programmers and the hardware that executes it. Understanding the structure, types, and encoding of machine instructions is therefore foundational to the study of computer organization and architecture.

Our study will focus on the design of instruction formats, the classification of instructions into functional groups, and the methods by which these low-level commands are used to implement higher-level programming constructs. We will see that the design of an instruction set involves a series of critical trade-offs between complexity, performance, and code density. For the GATE examination, a firm grasp of how an instruction is encoded into a binary format and how sequences of instructions manipulate data in registers and memory is of paramount importance.

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Key Concepts

1. Components of an Instruction

Every machine instruction can be deconstructed into two primary components: the operation code and the operands.

* Opcode (Operation Code): This field specifies the operation to be performed, such as addition (`ADD`), data transfer (`LOAD`), or a conditional branch (`BEQ`). The number of bits allocated to the opcode determines the maximum number of unique instructions the processor can support. If an opcode field has $k$ bits, it can represent up to $2^k$ distinct instructions.

* Operands: These fields specify the source and destination of the data for the operation. An operand can be a processor register, a memory address, or an immediate value embedded directly within the instruction itself. The structure and number of operand fields define the instruction format.

Consider a simple conceptual instruction `ADD R1, R2, R3`, which performs the operation $R1 \leftarrow R2 + R3$. Here, `ADD` is the operation, while $R1$, $R2$, and $R3$ are the operands (specifically, register operands).

Opcode
Operand(s)

2. Instruction Format Design

The layout of an instruction in its binary form is known as its instruction format. The design of this format is a critical aspect of ISA design, involving a balance between instruction length, functionality, and the number of available registers and instructions. For a fixed-length instruction of $N$ bits, these bits must be partitioned among the opcode and various operand fields.

A crucial detail in these calculations is determining the number of bits required to represent a certain number of items. To represent $M$ distinct items (e.g., instructions or registers), we require at least $\lceil \log_2 M \rceil$ bits.

Worked Example:

Problem: A processor has a 32-bit instruction format. The ISA supports 60 distinct instructions and has 32 general-purpose registers. If an instruction format needs to specify two source registers and one destination register, what is the maximum number of bits available for an immediate operand in this format?

Solution:

Step 1: Calculate the bits required for the opcode.
The processor supports 60 instructions. The number of bits required for the opcode is:

Step 2: Calculate the bits required for each register operand.
The processor has 32 registers. The number of bits to uniquely identify one register is:

Step 3: Calculate the total bits used by the opcode and the three register fields.
The instruction specifies one destination and two source registers.

Step 4: Calculate the remaining bits for the immediate operand.
The total instruction length is 32 bits.

Answer: A maximum of $11$ bits are available for the immediate operand.

3. Instruction Types and Formats

Architectures often employ multiple instruction formats to efficiently encode different types of operations. A common classification is based on the location of operands, leading to formats like R-type (Register-type) and I-type (Immediate-type).

* R-type (Register-type): These instructions perform operations among processor registers. A typical format includes an opcode and specifiers for source and destination registers.
* Example: `ADD $R1$, $R2$, $R3$`
* Format: `| Opcode | Dst Reg | Src1 Reg | Src2 Reg | ... |`

* I-type (Immediate-type): These instructions involve an immediate value that is part of the instruction itself.
* Example: `ADDI $R1$, $R2$, 100` (Add Immediate)
* Format: `| Opcode | Dst Reg | Src Reg | Immediate Value |`

This dual-format approach allows R-type instructions to have more register fields, while I-type instructions can dedicate a significant portion of their bits to a large constant value.

Worked Example:

Problem: A 32-bit processor has 64 registers and 120 instructions. The instructions are of two types: Type-A and Type-B. Type-A instructions are register-based and have three register operands. Type-B instructions have one register operand and an immediate field. The opcode field is of fixed size for all instructions. Calculate the maximum size of the immediate field in Type-B instructions.

Solution:

Step 1: Determine the size of the opcode field.
There are 120 instructions.

Step 2: Determine the size of a register specifier field.
There are 64 registers.

Step 3: Analyze the bit allocation for Type-A instructions.
This format must fit within 32 bits, but its structure helps confirm our field sizes.

This leaves $32 - 25 = 7$ unused bits in this format, which is permissible.

Step 4: Calculate the maximum size of the immediate field for Type-B instructions.
The total size is 32 bits. This format has an opcode, one register operand, and the immediate field.

Answer: The maximum size of the immediate field is $19$ bits.

4. Major Classes of Instructions

Instructions can be categorized based on their function. Understanding these classes helps in deciphering assembly code and its relation to high-level programs.

| Instruction Class | Description | Examples |
|-------------------|--------------------------------------------------------------------------|-------------------------------|
| Data Transfer | Move data between registers and memory, or between registers. | `LOAD`, `STORE`, `MOV` |
| Arithmetic | Perform arithmetic operations like addition, subtraction, multiplication.| `ADD`, `SUB`, `MUL`, `INC`, `DEC` |
| Logical | Perform bitwise operations like AND, OR, NOT, and shifts. | `AND`, `OR`, `XOR`, `SHL`, `SHR`|
| Control Flow | Alter the sequence of instruction execution. | `JMP`, `BEQ`, `BNZ`, `CALL`, `RET`|

The logical shift left (`SHL`) instruction is particularly noteworthy. A shift left by $k$ positions is equivalent to multiplication by $2^k$. This is a common optimization used by compilers. For instance, `x * 8` can be implemented as `SHL x, 3` since $8 = 2^3$.

5. Mapping High-Level Constructs to Assembly

High-level language constructs like loops and array accesses are translated by a compiler into a sequence of machine instructions.

* Array Access: Accessing an element $A[i]$ in a byte-addressable system requires calculating its memory address. If the base address of the array $A$ is stored in a register (e.g., $r_{base}$) and the index $i$ is in another (e.g., $r_{index}$), the address is computed as:

The multiplication is often implemented with a shift instruction if the element size is a power of two. For a 32-bit (4-byte) integer, this becomes $r_{base} + (r_{index} \ll 2)$.

* Loops: A `for` or `while` loop is typically implemented using:
1. An initialization of a loop counter.
2. A conditional branch instruction that checks the loop termination condition. If the condition is met, it branches to the code after the loop.
3. The body of the loop.
4. An instruction to update the loop counter.
5. An unconditional jump back to the start of the loop (to the conditional branch).

Worked Example:

Problem: Trace the execution of the following assembly snippet. Assume $R1$ is initialized to 3, $R2$ holds the base address of an integer array $M$ (4 bytes per element), which contains `{10, 20, 30, 40}`. $R3$ is initialized to 0. Memory is byte-addressable.

```assembly
LOOP: BEQ R1, R0, END ; Branch to END if R1 == R0 (R0 is always 0)
ADD R3, R3, M[R14] ; Semantically, R3 = R3 + Memory[Base(M)+R14]
DEC R1 ; R1 = R1 - 1
JMP LOOP
END: HALT
```

Solution:

We trace the state of registers $R1$ and $R3$ through each iteration.

Initial State:
$R1 = 3$, $R3 = 0$

Iteration 1:

`BEQ $R1$, $R0$, END`: $R1$ is 3, not 0. No branch.

`ADD $R3$, $R3$, $M[R1 \times 4]$`: $R1 \times 4 = 12$. Address is $\operatorname{Base}(M)+12$, which is $M[3]$. $M[3]$ is 40.

$R3$ becomes $0 + 40 = 40$.

`DEC $R1$`: $R1$ becomes $3 - 1 = 2$.

`JMP LOOP`: Go to the start.

State: $R1 = 2$, $R3 = 40$

Iteration 2:

`BEQ $R1$, $R0$, END`: $R1$ is 2, not 0. No branch.

`ADD $R3$, $R3$, $M[R1 \times 4]$`: $R1 \times 4 = 8$. Address is $\operatorname{Base}(M)+8$, which is $M[2]$. $M[2]$ is 30.

$R3$ becomes $40 + 30 = 70$.

`DEC $R1$`: $R1$ becomes $2 - 1 = 1$.

`JMP LOOP`: Go to the start.

State: $R1 = 1$, $R3 = 70$

Iteration 3:

`BEQ $R1$, $R0$, END`: $R1$ is 1, not 0. No branch.

`ADD $R3$, $R3$, $M[R1 \times 4]$`: $R1 \times 4 = 4$. Address is $\operatorname{Base}(M)+4$, which is $M[1]$. $M[1]$ is 20.

$R3$ becomes $70 + 20 = 90$.

`DEC $R1$`: $R1$ becomes $1 - 1 = 0$.

`JMP LOOP`: Go to the start.

State: $R1 = 0$, $R3 = 90$

Iteration 4:

`BEQ $R1$, $R0$, END`: $R1$ is 0. Condition is true. Branch to `END`.

`HALT`: Program terminates.

Answer: The final value in register $R3$ is $90$.

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Problem-Solving Strategies

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Common Mistakes

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Practice Questions

:::question type="MCQ" question="A processor's Instruction Set Architecture (ISA) explicitly defines which of the following?" options=["The number of stages in the instruction pipeline", "The technology used to implement the main memory (DRAM vs. SRAM)", "The set of addressing modes supported by the processor", "The size of the L1 data cache"] answer="The set of addressing modes supported by the processor" hint="The ISA is the abstract model visible to a programmer or compiler. Which of these options is part of that programming model?" solution="
Step 1: Analyze the options in the context of ISA vs. Microarchitecture.

• The number of pipeline stages is an implementation detail (microarchitecture) to improve performance, not part of the ISA.


• The memory technology (DRAM/SRAM) is a hardware implementation detail, not part of the ISA.


• The size of the L1 cache is a microarchitectural feature affecting performance, invisible to the programmer at the ISA level.


• Addressing modes define how instruction operands specify addresses. This is fundamental to how assembly code is written and is therefore a core part of the ISA.

Result: The set of addressing modes is part of the ISA.
"
:::

:::question type="NAT" question="A processor has a 40-bit instruction word. The instruction set consists of 200 instructions. The processor has 128 general-purpose registers. If an instruction format uses one opcode field, two source register fields, one destination register field, and the rest for an immediate value, the number of bits available for the immediate value is ________." answer="11" hint="Calculate the bits required for the opcode and the three register fields first, then subtract from the total instruction length." solution="
Step 1: Calculate the bits required for the opcode field.
Number of instructions = 200.

Step 2: Calculate the bits required for each register field.
Number of registers = 128.

Step 3: Calculate the total bits used by the opcode and three register fields.
There are two source registers and one destination register.

Step 4: Calculate the remaining bits available for the immediate value.
Total instruction length = 40 bits.

Result: The number of bits available for the immediate value is 11.
Answer: \boxed{11}
"
:::

:::question type="MSQ" question="For a typical modern processor, which of the following instructions, when executed, can potentially change the value of the Program Counter (PC) to a value other than PC + (instruction length)?" options=["An arithmetic instruction `ADD R1, R2, R3`", "A conditional branch instruction `BNE R4, R5, LABEL`", "A data transfer instruction `LOAD R6, 0(R7)`", "An unconditional jump instruction `JMP TARGET`"] answer="A conditional branch instruction `BNE R4, R5, LABEL`,An unconditional jump instruction `JMP TARGET`" hint="The Program Counter holds the address of the next instruction to be fetched. Which instructions are designed to alter the flow of control?" solution="

• An arithmetic instruction like `ADD` only modifies its destination register (`R1`). The PC is updated sequentially to point to the next instruction in memory (PC + instruction length). So, this is incorrect.


• A conditional branch instruction like `BNE` (Branch if Not Equal) explicitly changes the PC to the address `LABEL` if the condition (`R4 != R5`) is true. If false, the PC increments sequentially. Because it can change the PC non-sequentially, this is a correct option.


• A data transfer instruction like `LOAD` only moves data from memory to a register (`R6`). The PC is updated sequentially. So, this is incorrect.


• An unconditional jump instruction `JMP` always changes the PC to the target address. This is its primary purpose. So, this is a correct option.

"
:::

:::question type="NAT" question="A CPU has a 32-bit instruction format and 32 registers. The instruction set is divided into two types. Type-1 has 60 instructions and contains an opcode, one register operand, and an immediate operand. Type-2 has 15 instructions and contains an opcode and three register operands. A single, fixed-size opcode field is used for all instructions. The minimum size of the opcode field in bits is ________." answer="7" hint="The opcode field must be large enough to accommodate the total number of unique instructions from both types." solution="
Step 1: Calculate the total number of distinct instructions in the ISA.
The processor must be able to distinguish between all instructions of both types.

Step 2: Calculate the minimum number of bits required to encode all these unique instructions.
The size of the opcode field must be sufficient to represent 75 different operations.

Result: The minimum size of the opcode field is 7 bits.
Answer: \boxed{7}
"
:::

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Summary

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What's Next?

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Part 2: Addressing Modes

Introduction

In the design of a computer's central processing unit (CPU), the instruction set architecture (ISA) specifies the set of instructions the processor can execute. A fundamental aspect of any instruction is specifying the data, or operands, on which it will operate. The method by which an instruction specifies its operand(s) is known as its addressing mode. The choice of addressing modes has a significant impact on the instruction length, the complexity of the CPU control unit, and the overall efficiency of program execution.

We find that a variety of addressing modes are employed in modern processors to provide programming flexibility and to efficiently handle complex data structures such as arrays, pointers, and records. Understanding these modes is essential for comprehending how machine-level code interacts with memory and CPU registers. This chapter will systematically introduce the principal addressing modes, elucidating the mechanism by which each one calculates the final location of an operand, a location we formally term the Effective Address.

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Key Addressing Modes

We will now examine the most common addressing modes found in computer architectures. For each mode, we will define its operation and specify how the Effective Address is determined.

1. Immediate Addressing

In immediate addressing, the operand itself is included directly within the instruction. This mode is useful for initializing registers or variables with constant values. No memory access is required to fetch the operand, which results in very fast execution.

The operand is located in the address field of the instruction.
Let us denote the address field of the instruction as $A$. The operand is simply $A$.

Effective Address: Not applicable, as the operand is part of the instruction itself.
Operand = $A$

2. Register Addressing

In register addressing, the operand is stored in a CPU register. The address field of the instruction specifies which register holds the operand. Since accessing a register is significantly faster than accessing main memory, this mode is highly efficient.

The instruction contains a register identifier, $R$.

Effective Address: Not applicable. The operand is in a register.
Operand = Content of Register $R$, denoted as $C(R)$.

3. Direct (Absolute) Addressing

In direct addressing, the address field of the instruction contains the Effective Address of the operand. This provides a simple mechanism for accessing a fixed memory location.

The instruction contains a memory address, $A$.

4. Indirect Addressing

In indirect addressing, the address field of the instruction specifies the memory address of a pointer. This pointer, in turn, contains the Effective Address of the operand. This mode requires two memory accesses: one to fetch the address of the operand, and a second to fetch the operand itself.

The instruction contains an address, $A$, which points to the location of the Effective Address.

Instruction

LOAD

1000

Main Memory

1000

2500

...

2500

Operand

1. Address of Pointer
2. Address of Operand

5. Register Indirect Addressing

This mode is a variation of indirect addressing where the address of the operand is held in a CPU register, rather than a memory location. The instruction specifies the register that contains the pointer to the operand.

The instruction contains a register identifier, $R$.

6. Indexed Addressing

Indexed addressing is particularly useful for accessing elements of an array. The Effective Address is calculated by adding the content of an index register to a base address (which is part of the instruction).

The instruction contains an address field $A$ and specifies an index register $IX$.

Worked Example:

Problem: An instruction `LOAD 2000($R1$)` uses indexed addressing. The memory location `2000` is the base address, and register $R1$ is the index register. If $R1$ contains the value `100`, what is the effective address of the operand?

Solution:

Step 1: Identify the components from the instruction and given data.

Base Address $A = 2000$
Index Register $IX = R1$
Content of Index Register $C(R1) = 100$

Step 2: Apply the formula for indexed addressing.

Step 3: Substitute the values into the formula.

Step 4: Compute the final Effective Address.

Answer: \boxed{2100}

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Problem-Solving Strategies

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Common Mistakes

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Practice Questions

:::question type="MCQ" question="An instruction uses an addressing mode where the operand is fetched from the memory location whose address is the sum of the program counter and the address field of the instruction. What is this addressing mode called?" options=["Indexed addressing","Base register addressing","Relative addressing","Indirect addressing"] answer="Relative addressing" hint="Consider how the Program Counter ($PC$) is used to calculate the target address for branch instructions." solution="The effective address is calculated as

This is the definition of Relative Addressing, commonly used for implementing branches and loops in a position-independent manner.
Answer: \boxed{\text{Relative addressing}}"
:::

:::question type="NAT" question="A processor uses indexed addressing. An instruction is stored at memory location 500. The address field of the instruction is 900. The index register contains the value 40. The effective address of the operand is ___." answer="940" hint="The location of the instruction itself (500) is irrelevant for calculating the $EA$ in indexed mode." solution="
Step 1: Identify the given values for indexed addressing.
Base Address (from instruction's address field) $A = 900$.
Content of Index Register $C(IX) = 40$.

Step 2: Apply the indexed addressing formula.

Step 3: Substitute the values and calculate.

Answer: \boxed{940}
"
:::

:::question type="MSQ" question="Which of the following addressing modes require at least one memory access to fetch the operand?" options=["Immediate addressing","Register addressing","Direct addressing","Indirect addressing"] answer="Direct addressing,Indirect addressing" hint="Consider which modes involve an operand that resides in main memory versus within the CPU or the instruction itself." solution="

• Immediate addressing: The operand is part of the instruction. No memory access is needed.


• Register addressing: The operand is in a CPU register. No memory access is needed.


• Direct addressing: The instruction contains the address of the operand in memory. This requires one memory access to fetch the operand.


• Indirect addressing: The instruction contains the address of a pointer in memory. This requires one memory access to get the pointer, and a second memory access to get the operand. Thus, it requires at least one (in fact, two) memory accesses.

Therefore, Direct and Indirect addressing require memory access.
Answer: \boxed{\text{Direct addressing, Indirect addressing}}"
:::

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Summary

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What's Next?

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Chapter Summary

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Chapter Review Questions

:::question type="MCQ" question="A processor's 16-bit instructions are encoded using an expanding opcode scheme. There are three types of instructions: 2-address, 1-address, and 0-address. Each address field is 4 bits long. If there are 250 two-address instructions and 92 one-address instructions, what is the maximum number of zero-address instructions that can be supported?" options=["16", "32", "48", "64"] answer="D" hint="Calculate the number of unused opcode patterns at each level. These 'escape codes' become the prefixes for the next level of instructions." solution="
This problem requires an understanding of expanding opcodes.

Step 1: Analyze the 2-Address Instructions.

• Instruction length ($L$) = 16 bits.


• Each address field ($A$) = 4 bits.


• Format: `Opcode | Address 1 (4) | Address 2 (4)`


• Number of bits available for the opcode = $L - 2A = 16 - 2 \times 4 = 8$ bits.


• Total possible patterns for an 8-bit opcode = $2^8 = 256$.


• We need to encode 250 two-address instructions.


• Number of unused 8-bit opcode patterns (escape codes) = $256 - 250 = 6$. These 6 patterns can be used as prefixes for the 1-address instructions.

Step 2: Analyze the 1-Address Instructions.

• The opcode for a 1-address instruction will be formed by one of the 6 escape codes followed by additional bits.


• Format: `Escape Code (8) | Opcode' (4) | Address (4)`


• The total length of the 1-address opcode (prefix + Opcode') must be $L - A = 16 - 4 = 12$ bits.


• Since the escape code is 8 bits, the `Opcode'` field has $12 - 8 = 4$ bits.


• Total possible 1-address instruction slots = (Number of 8-bit escape codes) $\times 2^{\text{bits in Opcode'}}$


• Total possible 1-address instruction slots = $6 \times 2^4 = 6 \times 16 = 96$.


• We are given that there are 92 one-address instructions.


• Number of unused 12-bit patterns (escape codes for 0-address instructions) = $96 - 92 = 4$.

Step 3: Analyze the 0-Address Instructions.

• The opcode for a 0-address instruction will be one of the 4 unused 12-bit patterns from the 1-address level, extended to 16 bits.


• A 0-address instruction uses all 16 bits for its opcode. Its prefix is 12 bits long. The remaining bits are $16 - 12 = 4$.


• Maximum number of 0-address instructions = (Number of unused 12-bit patterns) $\times 2^{\text{remaining bits}}$


• Maximum number of 0-address instructions = $4 \times 2^4 = 4 \times 16 = 64$.

Answer: \boxed{64}"
:::

:::question type="NAT" question="Consider a machine with a byte-addressable memory of $2^{20}$ bytes. The machine has a register file of 32 registers. An instruction `SUB R1, 250(R2)` is stored at memory location 1000. At the beginning of its execution, the program counter (PC) holds 1000, register R1 holds the value 500, and register R2 holds the value 4000. The content of memory location 4250 is 350. The instruction performs the operation R1 ← R1 - M[250 + R2]. What is the value in register R1 after the instruction is executed?" answer="150" hint="First, calculate the effective address ($EA$) of the memory operand using the base-displacement addressing mode. Then, fetch the operand and perform the subtraction." solution="
The problem requires us to trace the execution of a single instruction involving base-displacement (or indexed) addressing.

Step 1: Identify the Addressing Mode and Operands.

• The instruction is `SUB R1, 250(R2)`.


• The destination operand is register $R1$.


• The source operand is a memory location specified by the addressing mode `250(R2)`. This is base-displacement addressing, where $R2$ is the base register and 250 is the displacement (or offset).

Step 2: Calculate the Effective Address ($EA$).

• The effective address is the sum of the contents of the base register and the displacement.


• Content of $R2 = 4000$.


• Displacement = 250.

Step 3: Fetch the Source Operand.

• The source operand is the value stored at the effective address in memory.


• We are given that the content of memory location 4250 is 350. So, $M[4250] = 350$.

Step 4: Perform the Operation.

• The operation is $R1 \leftarrow R1 - M[EA]$.


• Initial value of $R1 = 500$.


• Value from memory, $M[4250] = 350$.

Answer: \boxed{150}
"
:::

:::question type="MCQ" question="Which of the following statements is LEAST characteristic of a typical RISC architecture when compared to a CISC architecture?" options=["Instructions are of a fixed length and possess a regular format.", "A large number of general-purpose registers are provided to minimize memory traffic.", "Complex addressing modes like 'auto-increment indirect' are synthesized using sequences of simpler instructions.", "Instruction execution is often managed by a microprogrammed control unit to handle operational complexity."] answer="D" hint="Consider the core design philosophies of RISC (simplicity, speed) and CISC (complexity, power). How does the control unit implementation reflect these philosophies?" solution="
Let us analyze each statement in the context of RISC vs. CISC design principles.

• A: Instructions are of a fixed length and possess a regular format. This is a hallmark of RISC design. Fixed-length instructions simplify the instruction fetch and decode stages of a pipeline, contributing to faster execution. This statement is characteristic of RISC.

• B: A large number of general-purpose registers are provided to minimize memory traffic. This is another key feature of RISC. By keeping operands in a large register file, the frequency of slow memory load and store operations is reduced. This is characteristic of RISC.

• C: Complex addressing modes like 'auto-increment indirect' are synthesized using sequences of simpler instructions. RISC architectures deliberately omit complex addressing modes. To achieve the same functionality, a compiler would generate a sequence of simple instructions (e.g., a load, an add, a store). This is characteristic of RISC.

• D: Instruction execution is often managed by a microprogrammed control unit to handle operational complexity. This is the defining characteristic of a CISC architecture. The complexity and variable nature of CISC instructions make a hardwired control unit impractical. Instead, a microprogram (a sequence of micro-instructions) stored in a control store (ROM) is used to interpret and execute each machine instruction. RISC architectures, with their simple and uniform instructions, are ideally suited for faster hardwired control units.

Therefore, the use of a microprogrammed control unit is least characteristic of a RISC architecture. Answer: \boxed{D}" :::

:::question type="NAT" question="A 2 GHz processor executes a program with $1 \times 10^6$ instructions. The instructions are categorized into three classes: Class A (ALU operations), Class B (Load/Store), and Class C (Branch). The instruction mix and cycles per instruction (CPI) for each class are given below. What is the total execution time of the program in microseconds (µs)?

| Class | CPI | Mix |
|---|---|---|
| A | 1 | 40% |
| B | 3 | 30% |
| C | 2 | 30% |
" answer="950" hint="First, calculate the average $CPI$ for the program based on the instruction mix. Then, use the average $CPI$ and instruction count to find the total number of clock cycles. Finally, use the clock rate to find the execution time." solution="
The total execution time of a program can be calculated using the formula:

Step 1: Calculate the Average CPI.
The average CPI is the weighted average of the CPI for each instruction class, where the weights are their frequencies in the instruction mix.

Step 2: Calculate the Total Number of Clock Cycles.

Step 3: Calculate the Execution Time.
The clock rate is $2 \text{ GHz}$, which is $2 \times 10^9$ cycles per second.

Step 4: Convert to Microseconds.
The question asks for the time in microseconds (µs). Since $1 \text{ s} = 10^6 \text{ µs}$:

Answer: \boxed{950}"
:::

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What's Next?