CPU Components

Overview

Having established the fundamental instruction set architecture, we now delve into the internal organization of the Central Processing Unit (CPU), the engine that executes the programs. This chapter dissects the CPU into its principal functional units, providing a detailed examination of the hardware structures responsible for computation and control. A mastery of these core components is not merely an academic exercise; it is fundamental to understanding processor performance, a topic of paramount importance in the GATE examination. Questions frequently test the candidate's ability to analyze the time taken for instruction execution, which is directly dependent on the underlying data-path and control logic.

We shall explore the two primary constituents of the processor: the data-path and the control unit. The data-path, which includes the Arithmetic Logic Unit (ALU) and the register file, can be conceptualized as the "brawn" of the CPU, containing the operational hardware required to store and manipulate data. The control unit, in contrast, serves as the "brain," interpreting instructions and generating the timed sequence of signals that orchestrate the activities within the data-path. By understanding this division of labor, we can systematically analyze how an instruction is fetched, decoded, executed, and how the results are stored, thereby building a complete picture of the instruction execution cycle from a hardware perspective.

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Chapter Contents

| # | Topic | What You'll Learn |
|---|-------|-------------------|
| 1 | ALU and Data-Path | The hardware for processing data. |
| 2 | Control Unit | Logic for orchestrating instruction execution. |

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Learning Objectives

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We now turn our attention to the ALU and Data-Path...
## Part 1: ALU and Data-Path

Introduction

The Central Processing Unit (CPU) is the locus of computation within any computer system. Its ability to execute instructions is predicated on a sophisticated arrangement of hardware components. We refer to this arrangement as the processor's data-path, which comprises the functional units responsible for storing and manipulating data. At the heart of the data-path lies the Arithmetic Logic Unit (ALU), the component that performs the actual computations.

Understanding the data-path is fundamental to comprehending how a processor executes instructions. It is the physical implementation of the operations specified by an instruction set architecture. The flow of data between registers, through the ALU, and back to registers is a meticulously orchestrated process governed by control signals. For the GATE examination, a clear grasp of data-path components and their interactions is essential for analyzing processor performance and functionality. We shall explore the constituent elements of a typical data-path, focusing on how they are interconnected to facilitate the execution of arithmetic and logical instructions.

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Key Components of a Data-Path

A data-path is not a monolithic entity but rather an assembly of distinct, well-defined hardware components. Let us examine the principal elements.

## 1. The Arithmetic Logic Unit (ALU)

The ALU is the computational core of the processor. It is a combinational digital circuit that performs a set of arithmetic operations (such as addition, subtraction, increment) and a set of logical operations (such as AND, OR, NOT, XOR) on integer binary numbers.

An ALU typically takes two operands as input, which we may denote as $A$ and $B$. It also receives a set of control signals, often called an ALUop or function code, which specifies which operation to perform. The output is the result of the computation, along with a set of status flags (e.g., Zero, Carry, Overflow) that provide information about the outcome.

ALU



A (Operand)


B (Operand)



ALU Control



Result



Flags

If an ALU has $k$ control lines, it can be configured to perform up to $2^k$ distinct operations.

## 2. Registers

Registers are high-speed storage locations within the CPU. They are essential for holding operands before an operation and for storing the result after an operation. The collection of general-purpose registers available to the programmer is often referred to as the register file.

A register file can be viewed as a small, very fast memory. It typically has read ports and write ports. For an operation like `ADD R3, R1, R2`, the register file must be able to read the contents of two registers (R1 and R2) simultaneously and write to a third register (R3). This is achieved with multiple read ports and a single write port, controlled by register addresses and a write-enable signal.

## 3. Multiplexers (MUX)

A multiplexer is a critical component for routing data within the data-path. It is a combinational circuit that selects one of several input signals and forwards the selected input to a single output line. The selection is directed by a set of control inputs, known as select lines.

A MUX with $2^n$ data inputs requires $n$ select lines to uniquely address each input. In a data-path, multiplexers are used to select the source of an operand for the ALU. For instance, an ALU input might come from the register file or from an immediate value embedded in the instruction itself. A MUX placed at the ALU input makes this selection possible.

Worked Example:

Problem: A processor data-path must select an operand for the ALU's 'A' input. The source can either be the content of register `R1` or a 16-bit immediate value `imm`. Design the MUX configuration for this selection.

Solution:

Step 1: Identify the number of inputs to the multiplexer.
We have two possible sources for the operand: `R1` and `imm`. Therefore, the number of inputs is 2. We require a 2-to-1 MUX.

Step 2: Determine the number of select lines required.
Using the formula $N_{inputs} = 2^n$, we have $2 = 2^n$.

A single select line, let us call it `ALUSrcA`, is needed.

Step 3: Define the MUX behavior based on the select line.
We can assign the behavior as follows:

• If `ALUSrcA` = 0, the MUX selects the output from the register file (content of `R1`).


• If `ALUSrcA` = 1, the MUX selects the immediate value.

This configuration is illustrated below.

MUX

From R1
0


Immediate Value
1

ALUSrcA

To ALU Input A

Answer: A 2-to-1 MUX controlled by a single select line is required to choose between the register value and the immediate value.

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Analyzing a Data-Path

To determine the capabilities of a given data-path, one must trace the possible routes that data can take. The presence of multiplexers creates decision points where different sources can be selected. By considering all possible combinations of MUX selections, we can deduce the full range of operations the hardware can support.

Consider the data-path shown below, which is a simplified model for executing arithmetic instructions.

Register File
Read Addr 1
Read Data 1
Read Addr 2
Read Data 2

Immediate

Mux_B

ALU

Write to Register

Reg/Imm Select

In this diagram, the first ALU operand is always sourced from `Read Data 1` of the register file. The second operand, however, is selected by `Mux_B`. It can be either `Read Data 2` from the register file or an external `Immediate` value.

This architecture supports two major classes of operations:

Register-Register Operations: The control signal `Reg/Imm Select` is set to choose the input from `Read Data 2`. The ALU then computes $( \text{Read Data 1} ) \operatorname{op} ( \text{Read Data 2} )$. This corresponds to instructions like `ADD R3, R1, R2`.

Register-Immediate Operations: The control signal `Reg/Imm Select` is set to choose the `Immediate` input. The ALU computes $( \text{Read Data 1} ) \operatorname{op} ( \text{Immediate} )$. This corresponds to instructions like `ADDI R2, R1, 100`.

Notice that an operation involving two immediate values is not possible with this particular data-path, as the first ALU input is hardwired to the register file output.

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Problem-Solving Strategies

When faced with a data-path diagram in GATE, the objective is usually to determine its capabilities or to calculate performance metrics.

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Common Mistakes

Students often make predictable errors when analyzing data-path diagrams. Being aware of these can prevent loss of marks.

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Practice Questions

:::question type="MCQ" question="A processor's data-path has an ALU that can perform 16 distinct operations. What is the minimum number of control lines required for this ALU?" options=["3","4","5","16"] answer="4" hint="The number of operations is related to the number of control lines by a power of 2." solution="
Step 1: Let $N$ be the number of distinct operations and $k$ be the number of control lines. The relationship is $N \le 2^k$.

Step 2: We are given $N = 16$. We need to find the minimum $k$ such that $16 \le 2^k$.

Step 3: We can write 16 as a power of 2.

Step 4: From the inequality, it is clear that the minimum integer value for $k$ is $4$.

Result: A minimum of $4$ control lines are required.
Answer: \boxed{4}
"
:::

:::question type="NAT" question="In a certain data-path, executing a register-immediate instruction involves the following sequential delays: Register File Read (2 ns), MUX delay (1 ns), ALU operation (5 ns), and Register File Write (2 ns). Calculate the minimum clock cycle time (in ns) required to execute this instruction." answer="10" hint="The minimum clock cycle time must be at least as long as the total delay of the longest path in the data-path for that instruction." solution="
Step 1: The total delay for the instruction is the sum of the delays of all components in the execution path.

Step 2: The path is given as: Register Read → MUX → ALU → Register Write.

Step 3: Sum the individual delays.

Result: The minimum clock cycle time required is $10 \text{ ns}$.
Answer: \boxed{10}
"
:::

:::question type="MSQ" question="Consider the data-path shown in the figure. RA, RB, and RZ are registers. Mux_A has inputs from RA and a constant value 0. Mux_B has inputs from RB and a constant value 1. Which of the following operations can be directly implemented by this data-path?

" options=["$RZ = RA + RB$","$RZ = RA + 1$","$RZ = 0 - RB$","$RZ = 0 + 1$"] answer="$RZ = RA + RB$, $RZ = RA + 1$, $RZ = 0 - RB$, $RZ = 0 + 1$" hint="Systematically check all four combinations of inputs possible from Mux_A and Mux_B." solution="
Let's analyze the possible inputs to the ALU.
ALU Input 1 can be selected from {$RA$, $0$} via Mux_A.
ALU Input 2 can be selected from {$RB$, $1$} via Mux_B.
The ALU can perform addition $(+)$ or subtraction $(-)$.

We check each option:

$RZ = RA + RB$: Select $RA$ from Mux_A and $RB$ from Mux_B. Perform ADD operation in ALU. This is possible.

$RZ = RA + 1$: Select $RA$ from Mux_A and the constant $1$ from Mux_B. Perform ADD operation. This is possible.

$RZ = 0 - RB$: Select the constant $0$ from Mux_A and $RB$ from Mux_B. Perform SUBTRACT operation. This is possible.

$RZ = 0 + 1$: Select the constant $0$ from Mux_A and the constant $1$ from Mux_B. Perform ADD operation. This is possible.

Since all four operations can be realized by setting the MUX select lines and ALU control appropriately, all options are correct.
Answer: \boxed{$RZ = RA + RB$, $RZ = RA + 1$, $RZ = 0 - RB$, $RZ = 0 + 1$}
"
:::

:::question type="MCQ" question="A digital system uses a 32-to-1 multiplexer. How many select lines are required for this MUX?" options=["32","1","5","6"] answer="5" hint="Recall the formula relating the number of inputs to the number of select lines." solution="
Step 1: The number of inputs to the multiplexer is $N_{inputs} = 32$.

Step 2: The number of select lines, $n$, is given by $n = \log_2(N_{inputs})$.

Step 3: Calculate the logarithm.

Result: $5$ select lines are required.
Answer: \boxed{5}
"
:::

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Summary

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What's Next?

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Part 2: Control Unit

Introduction

The Central Processing Unit (CPU) is composed of several fundamental components, and at its very heart lies the Control Unit (CU). The CU acts as the central nervous system of the processor, directing and coordinating the activities of the entire computer system. It does not execute program instructions itself; rather, it interprets them and generates a sequence of timed control signals that command other components—such as the Arithmetic Logic Unit (ALU), memory, and I/O devices—to perform their specific tasks.

Our study of the Control Unit will focus on the two primary design philosophies for its implementation: hardwired and microprogrammed. Understanding the architectural differences, performance characteristics, and trade-offs between these two approaches is essential for a comprehensive grasp of computer organization. We shall see that the choice of control unit design has profound implications for the processor's instruction set architecture, speed, and flexibility.

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Key Concepts

The implementation of a Control Unit can be broadly classified into two distinct categories. Let us examine each in detail.

1. Hardwired Control Unit

A hardwired control unit is implemented as a finite state machine using sequential and combinatorial logic circuits. The control signals are generated by a physical hardware configuration of gates, flip-flops, and decoders. For a given instruction, the opcode is fed into a logic circuit that produces the corresponding sequence of control signals required for its execution.

The primary advantage of this approach is speed. Since the control signals are generated directly by dedicated hardware logic, the operational latency is minimized. However, this comes at the cost of flexibility. Modifying the instruction set or correcting a design flaw requires redesigning and refabricating the physical circuitry, which is a complex and expensive undertaking. This design is characteristic of Reduced Instruction Set Computer (RISC) architectures, which prioritize execution speed and have simpler, more regular instruction sets.

Hardwired vs. Microprogrammed Control Unit

Hardwired Control

Instruction Register (IR)


Combinational
Logic Circuit

Control Signals

Flags, Clock

Microprogrammed Control

Instruction Register (IR)

Sequencer

Control Memory
(ROM)

Control Signals

2. Microprogrammed Control Unit

In contrast, a microprogrammed control unit generates control signals based on a program stored in a special, high-speed memory called the Control Memory or Control Store (typically a ROM). Each instruction from the main memory causes the processor to execute a sequence of one or more micro-instructions from the Control Memory. Each micro-instruction specifies a set of control signals to be activated during a single clock cycle.

This design offers significant flexibility. The instruction set can be modified by simply updating the microprogram in the Control Memory, without any hardware changes. This approach simplifies the design of complex instruction sets and is thus characteristic of Complex Instruction Set Computer (CISC) architectures. The trade-off, however, is performance. Fetching micro-instructions from the Control Memory introduces an additional memory access step, making this design inherently slower than its hardwired counterpart.

A critical parameter in this design is the size of the Control Memory.

Worked Example:

Problem: A microprogrammed control unit has a control memory with 2048 words. Each micro-instruction is 32 bits wide. Calculate the total size of the control memory in kilobytes (KB), assuming $1 \text{ KB} = 2^{10} \text{ bytes}$.

Solution:

Step 1: Identify the given parameters.
Number of micro-instructions (words), $N = 2048$.
Width of a micro-instruction, $W = 32$ bits.

Step 2: Apply the formula for Control Memory size in bits.

Step 3: Perform the calculation.

Step 4: Convert the size from bits to bytes and then to kilobytes.
Recall that 1 byte = 8 bits.

Now, convert to kilobytes, where $1 \text{ KB} = 2^{10} \text{ bytes}$.

Result:

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Problem-Solving Strategies

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Common Mistakes

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Practice Questions

:::question type="MCQ" question="Which of the following statements most accurately describes a primary advantage of a hardwired control unit over a microprogrammed control unit?" options=["It simplifies the design of complex instruction sets.","It offers greater flexibility for modifying the instruction set.","It provides faster execution of instructions.","It requires less complex hardware for implementation."] answer="It provides faster execution of instructions." hint="Consider the implementation of each control unit type. One uses direct logic circuits while the other involves memory access." solution="A hardwired control unit is implemented using combinatorial logic circuits. This allows for the generation of control signals with minimal delay, leading to faster instruction execution. In contrast, a microprogrammed unit must fetch micro-instructions from a control memory, which introduces latency. Flexibility and ease of designing complex instruction sets are advantages of microprogrammed control, not hardwired."
:::

:::question type="NAT" question="A processor's control unit is microprogrammed. The control memory contains 4096 micro-instructions. The micro-instruction format has a 4-bit opcode field, a 12-bit address field, and a 16-bit field for controlling various hardware units. What is the size of the control memory in Kilobits (Kbits)?" answer="128" hint="First, calculate the total width of a single micro-instruction. Then, use the formula for control memory size. Remember the question asks for Kbits, not KBytes." solution="Step 1: Calculate the width (W) of one micro-instruction by summing the widths of its fields.

Step 2: Identify the number of micro-instructions (N).

Step 3: Calculate the total size of the Control Memory (CM) in bits.

Step 4: Convert the size from bits to Kilobits (Kbits). Note that $1 \text{ Kbit} = 1024 \text{ bits} = 2^{10} \text{ bits}$.

Result:

Answer: \boxed{128 \text{ Kbits}} " :::

:::question type="MSQ" question="Which of the following characteristics are typically associated with a microprogrammed control unit?" options=["Found in CISC architectures.","Slower operation compared to a hardwired unit.","Difficult to add new instructions.","Control signals are stored in a Read-Only Memory (ROM)."] answer="Found in CISC architectures.,Slower operation compared to a hardwired unit.,Control signals are stored in a Read-Only Memory (ROM)." hint="Evaluate each statement based on the core principles of microprogramming. Think about the trade-offs: flexibility versus speed." solution="

• Found in CISC architectures: Correct. Microprogramming simplifies the implementation of the large and complex instruction sets found in CISC processors.


• Slower operation compared to a hardwired unit: Correct. The overhead of fetching micro-instructions from the control memory makes it slower than a hardwired unit that uses direct logic.


• Difficult to add new instructions: Incorrect. This is a characteristic of hardwired control. Microprogrammed control is flexible, and new instructions can be added by updating the microprogram in the control store.


• Control signals are stored in a Read-Only Memory (ROM): Correct. The microprogram, which encodes the control signals, is stored in a special, high-speed memory, which is typically a ROM, known as the control store or control memory.

"
:::

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Summary

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What's Next?

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Chapter Summary

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Chapter Review Questions

:::question type="MCQ" question="For a conditional branch instruction, such as `BNE` (Branch on Not Equal), which of the following components are most critically involved in the decision-making and execution process of the branch itself?" options=["The ALU, the Program Counter (PC), and the Control Unit","The Instruction Register (IR) and the Memory Address Register (MAR) only","The ALU and the Memory Data Register (MDR) only","The microprogram sequencer and the system clock"] answer="A" hint="Consider which unit performs the comparison, which unit holds the result of that comparison (as a status flag), which unit makes the decision based on that flag, and which register must be updated to change the flow of execution." solution="The execution of a `BNE` instruction involves several cooperative steps that span the major CPU components.

Comparison: The condition for the branch (e.g., comparing two registers to see if they are not equal) is typically evaluated by the ALU. The ALU performs a subtraction, and if the result is zero, the Zero Flag (Z) in the status register is set to 1. If the result is non-zero, the Z flag is cleared to 0.

Decision: The Control Unit decodes the `BNE` opcode. Its logic is designed to check the state of the Zero Flag. For `BNE`, the control unit will initiate the branch if and only if the Z flag is 0.

Execution: If the branch condition is met (Z=0), the control unit generates signals to load the branch target address into the Program Counter (PC). If the condition is not met (Z=1), the control unit allows the PC to be incremented to the next sequential instruction.

Therefore, the ALU (to set the flag), the Control Unit (to make the decision), and the PC (to be updated) are all critically involved. The other options are incorrect as they omit one or more of these essential components in the decision-making logic.
"
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:::question type="NAT" question="A processor with a single-bus data-path has a clock rate of 2 GHz. An ALU operation takes 2 clock cycles. A memory read or write operation takes 5 clock cycles. Any other internal register transfer (e.g., moving data from register to bus, or bus to register) takes 1 clock cycle. Calculate the total time in nanoseconds (ns) required to execute the instruction `ADD R1, [R2]`, which adds the content of the memory location pointed to by register R2 to register R1, storing the result in R1. Assume the instruction has already been fetched and decoded." answer="6" hint="Break the instruction `R1 <- [R1] + M[[R2]]` into its fundamental micro-operations. Sum the clock cycles for each step, remembering that on a single-bus architecture, only one data transfer can occur at a time." solution="Step 1: Calculate the clock cycle time.

The processor clock rate is $2 \text{ GHz}$, so the clock cycle time is:

Step 2: Break down the instruction `ADD R1, [R2]` into micro-operations and count cycles for a single-bus architecture.

The instruction `ADD R1, [R2]` means `R1 \leftarrow [R1] + M[[R2]]`.

Move address to MAR: The content of R2 is placed on the bus and latched into the MAR.

- `R2_{out}, MAR_{in}`: 1 clock cycle.

Memory Read: The memory unit performs a read operation. The data is then available in the MDR.

- `Memory Read`: 5 clock cycles.

Move memory data to temporary register: The data from MDR (the second operand) is moved to a temporary register, say Y.

- `MDR_{out}, Y_{in}`: 1 clock cycle.

Move R1 to ALU input A: The content of R1 (the first operand) is moved to an ALU input register.

- `R1_{out}, ALU\_A_{in}`: 1 clock cycle.

Move Y to ALU input B: The content of Y is moved to the other ALU input register.

- `Y_{out}, ALU\_B_{in}`: 1 clock cycle.

Perform ALU Addition: The ALU performs the addition, and the result is stored in an output buffer register, Z.

- `ALU\_Add, Z_{in}`: 2 clock cycles.

Store the Result: The result from the ALU output register Z is moved back to R1.

- `Z_{out}, R1_{in}`: 1 clock cycle.

Total Clock Cycles:

Step 3: Calculate the total execution time.

Answer: \boxed{6 \text{ ns}}
"
:::

:::question type="MCQ" question="Which of the following statements provides the most accurate distinction between hardwired and microprogrammed control units?" options=["A hardwired control unit uses a control store (ROM) to generate signals, making it more flexible than a microprogrammed unit.","A microprogrammed control unit is generally faster because microinstructions can be fetched in parallel with data operations.","The design and implementation of a hardwired control unit is less complex and faster than a microprogrammed unit for a CISC architecture.","A hardwired control unit generates control signals using fixed combinational logic circuits, offering higher speed, while a microprogrammed unit uses sequences of microinstructions, offering greater flexibility."] answer="D" hint="Focus on the core implementation technology of each control unit type and the resulting trade-off between performance and flexibility." solution="Let us analyze each option:

• A: This is incorrect. The microprogrammed control unit uses a control store (ROM or RAM), not the hardwired unit. This feature is what gives it flexibility.


• B: This is incorrect. The microprogrammed control unit is generally slower because fetching a microinstruction from the control store introduces an additional delay in the process of generating control signals.


• C: This is incorrect. For a Complex Instruction Set Computer (CISC) architecture, which has many complex instructions, designing the fixed combinational logic for a hardwired control unit is extremely difficult, error-prone, and time-consuming. A microprogrammed approach is far simpler to design and debug in this scenario.


• D: This statement accurately captures the fundamental trade-off. Hardwired control uses gates, flip-flops, and decoders—a fixed logic network—to produce control signals directly from the instruction register. This is very fast but rigid. Microprogrammed control translates each machine instruction into a series of smaller microinstructions stored in a control memory. This is more flexible (the instruction set can be changed by updating the microcode) but slower due to the overhead of fetching microinstructions.

"
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:::question type="NAT" question="In a single-bus CPU architecture, the micro-operation to fetch an operand from memory, `R2 <- M[R1]`, requires moving the address from R1 to the MAR, initiating a memory read, and then transferring the data from the MDR to R2. What is the minimum number of times the internal CPU bus must be used to transfer data between internal CPU registers (like R1, R2, MAR, MDR) to complete this entire operation?" answer="2" hint="The internal bus can only carry one piece of information at a time. Identify the distinct information transfers that must occur between the internal registers to get the address out to the memory system and the data back in from the memory system." solution="The operation is `R2 <- M[R1]`. Let's break this down into the required internal bus transfers.

Transfer Address to MAR: The address of the memory location is stored in register R1. To initiate a memory read, this address must be loaded into the Memory Address Register (MAR). On a single-bus architecture, this requires one use of the bus.

- Micro-operation: `MAR \leftarrow [R1]`
- Bus Usage: The content of R1 is placed on the bus, and the control unit asserts the `MAR_in` signal to latch it. This is 1 bus use.

Memory Read Operation: The control unit now issues a `Read` signal. The memory system takes some time to retrieve the data. Once retrieved, the data is placed in the Memory Data Register (MDR). This memory cycle itself does not necessarily tie up the internal CPU bus, but no further bus operations can proceed until the data is in the MDR.

Transfer Data to R2: The data fetched from memory now resides in the MDR. To complete the instruction, this data must be moved to the destination register, R2. This requires a second use of the bus.

- Micro-operation: `R2 \leftarrow [MDR]`
- Bus Usage: The content of MDR is placed on the bus, and the control unit asserts the `R2_in` signal. This is the 2nd bus use.

Therefore, a minimum of two separate transfers over the internal CPU bus are required to complete the operation.
"
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What's Next?