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Flip-Flops, Counters and Finite State Machines Short Notes for GATE CS

Flip-Flops, Counters and Finite State Machines short notes for GATE CS: 5 study cards covering concepts, formulas, shortcuts and exam traps, plus solved pract

flip flops counters and finite state machines short notes

Topic Summary: Sequential Circuit Analysis Checklist

.checklist-item { display: flex; align-items: flex-start; gap: 0.75rem; margin-bottom: 0.5rem; } .check-box { width: 16px; height: 16px; border: 2px solid var(--color-primary); border-radius: 3px; flex-shrink: 0; margin-top: 3px; } .equation-block { background: color-mix(in srgb, var(--color-text) 5%, transparent); padding: 1rem; border-radius: 6px; margin: 1rem 0; } Final Checklist Before Starting: Identified all flip-flops and types (D, JK, T, SR) Noted clock edge polarity (positive or negative) Recorded initial state correctly Analysis Steps: Written excitation equations for all flip-flop inputs Substituted into characteristic equations Derived next-state equations Tracing: Built state table (if helpful) Started from correct initial state Computed each transition carefully Stopped when pattern detected or state repeated Verification: Checked first transition manually Verified no calculation errors in XOR, AND, OR Confirmed cycle closure (if applicable) Characteristic Equations (Memorize) D: Q_{n e x t} = D JK: Q_{n e x t} = J \overline{Q} + \overline{K} Q T: Q_{n e x t} = T \oplus Q SR: Q_{n e x t} = S + \overline{R} Q (with S R = 0) If You See... Pattern Action MUX with feedback Write MUX equation, treat as FF input All T flip-flops Look for counter pattern Mixed FF types Apply correct equation per FF "Number of distinct states" Trace until repeat, count unique Negative-edge clock Same method, just note edge type You are ready for sequential circuit analysis problems.

Topic Summary: Counter Analysis Checklist

.checklist-item { display: flex; align-items: flex-start; gap: 0.75rem; margin-bottom: 0.75rem; } .check-box { width: 16px; height: 16px; border: 2px solid var(--color-primary); border-radius: 3px; flex-shrink: 0; margin-top: 3px; background: color-mix(in srgb, var(--color-primary) 10%, transparent); } Final Checklist 1. Identify the Architecture Ripple: Clock daisy-chained (Q or \overline{Q} to next CLK). Synchronous: All CLK pins tied to the same global clock. 2. Ripple Counter Direction (Negative-Edge FFs) UP: Next CLK connected to previous Q . DOWN: Next CLK connected to previous \overline{Q} . (Reverse these rules for Positive-Edge FFs). 3. Frequency & Delay Standard n -bit Ripple: f_{ma x} = \frac{1}{n \cdot t _{p d}} Truncated Ripple: f_{ma x} = \frac{1}{k \cdot t _{p d} + t _{g a t e}} (where k is the number of FFs that actually toggle during reset). Synchronous: f_{ma x} = \frac{1}{t _{p d} + t _{l o g i c}} 4. Synchronous Analysis Method Write excitation equation for each FF input (e.g., T_{1} = Q_{0}). Substitute into characteristic equation (e.g., Q_{1, n e x t} = T_{1} \oplus Q_{1}). Build state table starting from the given initial state. Trace until the sequence repeats or the required number of clocks is reached.

Final Revision Checklist

Final Revision Checklist Before you finalize your answer, run this checklist. If yes, your excitation equations are solid. ✓ Flip-Flop Type Verified Confirmed whether the problem specifies D, T, JK, or SR. ✓ Translation Accurate Q \to Q^{+} correctly mapped to excitation inputs using the standard table (especially checking X placements). ✓ K-Map Axes Correct Variables on the outside are Current State (Q), not Next State (Q^{+}). ✓ Don't Cares Utilized Unused states in the sequence are marked as X and aggressively grouped for simplification. ✓ Equation Form Final expressions are in minimal Sum of Products (SOP) or recognized XOR forms, matching the expected answer format.

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Question 1

Level 1: Warm-up

An SR flip-flop has two inputs S and R . One specific input combination is invalid (undefined output). What is the number of valid input combinations for the SR flip-flop?

Question 2

Level 1: Warm-up

For a JK flip-flop, the next state is given by the characteristic equation Q_{next} = J \overline{Q} + \overline{K} Q . The maximum number of input pairs (J, K) that guarantee Q_{next} = \overline{Q} for any initial state Q is

Question 3

Level 1: Warm-up

Consider a 3-bit ripple counter with flip-flop propagation delay of 20 ns and a strobe delay of 20 ns. Which of the following statements regarding its maximum operating frequency is true?

Question 4

Level 1: Warm-up

A sequential circuit has 2 D flip-flops and 2 external inputs. The complete state table lists every combination of current state and input values. How many rows does this state table contain?

Question 5

Level 1: Warm-up

A sequential circuit must be capable of representing at least 4 distinct states. What is the minimum number of flip-flops required?

Question 6

Level 1: Warm-up

A sequential circuit has 3 state variables and 2 external inputs. The output function of a Mealy machine depends on n + m variables, while a Moore machine depends on n variables. The difference in the number of variables the output function depends on between a Mealy and a Moore implementation of this circuit is

Question 7

Level 1: Warm-up

Consider a sequential circuit with three flip-flops: Q_{1} and Q_{2} are T flip-flops, and Q_{3} is a D flip-flop. The connections are T_{1} = Q_{2} \cdot Q_{3}, T_{2} = Q_{1}, and D_{3} = Q_{1} \oplus Q_{2} . The circuit is initialized to Q_{1} Q_{2} Q_{3} = 011 . Which of the following statements about the state sequence is true?

Question 8

Level 1: Warm-up

In an 8-bit synchronous counter, the propagation delay of each flip-flop is 15 ns and the maximum delay of the combinational logic is 25 ns. The maximum total propagation delay for any state transition is

Question 9

Level 1: Warm-up

Consider the following assertion and reason regarding a sequential circuit: Assertion (A): In a ripple counter built with negative-edge-triggered flip-flops, connecting the clock input of each stage to the \overline{Q} output of the previous stage results in a DOWN counter. Reason (R): When the current state bit transitions from 0 to 1, its \overline{Q} output transitions from 1 to 0, providing the required negative clock edge to trigger the next stage.

Question 10

Level 1: Warm-up

For a D flip-flop, the excitation input D is required to be equal to the next state Q^{+} . If the current state is Q = 1 and the desired next state is Q^{+} = 0, what is the value of the excitation input D ?

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Flip-Flops, Counters and Finite State Machines Short Notes for GATE CS

Flip-Flops, Counters and Finite State Machines short notes for GATE CS: 5 study cards covering concepts, formulas, shortcuts and exam traps, plus solved practice questions.

Topic Summary: Sequential Circuit Analysis Checklist

Final Checklist

Before Starting:

Identified all flip-flops and types (D, JK, T, SR)

Noted clock edge polarity (positive or negative)

Recorded initial state correctly

Analysis Steps:

Written excitation equations for all flip-flop inputs

Substituted into characteristic equations

Derived next-state equations

Tracing:

Built state table (if helpful)

Started from correct initial state

Computed each transition carefully

Stopped when pattern detected or state repeated

Verification:

Checked first transition manually

Verified no calculation errors in XOR, AND, OR

Confirmed cycle closure (if applicable)

Characteristic Equations (Memorize)

D: Q_{n e x t} = D

JK: Q_{n e x t} = J \overline{Q} + \overline{K} Q

T: Q_{n e x t} = T \oplus Q

SR: Q_{n e x t} = S + \overline{R} Q (with S R = 0)

If You See...

Pattern	Action
MUX with feedback	Write MUX equation, treat as FF input
All T flip-flops	Look for counter pattern
Mixed FF types	Apply correct equation per FF
"Number of distinct states"	Trace until repeat, count unique
Negative-edge clock	Same method, just note edge type

You are ready for sequential circuit analysis problems.

Topic Summary: Counter Analysis Checklist

Final Checklist

1. Identify the Architecture

Ripple: Clock daisy-chained (

Q

\overline{Q}

to next CLK).

Synchronous: All CLK pins tied to the same global clock.

2. Ripple Counter Direction (Negative-Edge FFs)

UP: Next CLK connected to previous $Q$ .

DOWN: Next CLK connected to previous $\overline{Q}$ .

(Reverse these rules for Positive-Edge FFs).

3. Frequency & Delay

Standard

n

-bit Ripple:

f_{ma x} = \frac{1}{n \cdot t _{p d}}

Truncated Ripple:

f_{ma x} = \frac{1}{k \cdot t _{p d} + t _{g a t e}}

(where

k

is the number of FFs that actually toggle during reset).

Synchronous:

f_{ma x} = \frac{1}{t _{p d} + t _{l o g i c}}

4. Synchronous Analysis Method

Write excitation equation for each FF input (e.g.,

T_{1} = Q_{0}

Substitute into characteristic equation (e.g.,

Q_{1, n e x t} = T_{1} \oplus Q_{1}

Build state table starting from the given initial state.

Trace until the sequence repeats or the required number of clocks is reached.

Final Revision Checklist

Before you finalize your answer, run this checklist. If yes, your excitation equations are solid.

✓

Flip-Flop Type Verified

Confirmed whether the problem specifies D, T, JK, or SR.

✓

Translation Accurate

$Q \to Q^{+}$ correctly mapped to excitation inputs using the standard table (especially checking $X$ placements).

✓

K-Map Axes Correct

Variables on the outside are Current State ( $Q$ ), not Next State ( $Q^{+}$ ).

✓

Don't Cares Utilized

Unused states in the sequence are marked as $X$ and aggressively grouped for simplification.

✓

Equation Form

Final expressions are in minimal Sum of Products (SOP) or recognized XOR forms, matching the expected answer format.

Final Revision Checklist

Before finalizing your design, run this checklist. If yes, your Mealy machine is correctly designed.

✓

Output Placement

Outputs are labeled on transitions (arrows), not inside states.

✓

Dependency Check

Output $Z$ is a function of both $Q$ and $X$ .

✓

Overlap Handling

Transitions that fail a sequence check for partial matches before resetting to $S_{0}$ .

✓

State Minimality

Verified that no two states are redundant (Mealy machines often have fewer states than Moore equivalents).

✓

Timing Awareness

Acknowledged that outputs may change asynchronously with input changes, potentially causing glitches if not synchronized.

Flip-Flops, Counters and Finite State Machines: Solved Questions with Step-by-Step Explanations (10 Problems)

Question 1 · Digital Logic MCQ

An SR flip-flop has two inputs $S$ and $R$ . One specific input combination is invalid (undefined output). What is the number of valid input combinations for the SR flip-flop?

A.
2
B.
3
C.
4
D.
5

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct recall of the SR flip-flop characteristic table.

Step 1: An SR flip-flop has two binary inputs, $S$ and $R$ . The total number of input combinations is $2^{2} = 4$ : namely $(0, 0), (0, 1), (1, 0), (1, 1)$ .

Step 2: From the characteristic table:

$S = 0, R = 0$ : Hold (valid)
$S = 0, R = 1$ : Reset (valid)
$S = 1, R = 0$ : Set (valid)
$S = 1, R = 1$ : Undefined / Invalid

Step 3: Excluding the one invalid combination $(1, 1)$ , the number of valid combinations is $4 - 1 = 3$ .

Answer: B

Question 2 · Digital Logic MCQ

For a JK flip-flop, the next state is given by the characteristic equation $Q_{next} = J \overline{Q} + \overline{K} Q$ . The maximum number of input pairs $(J, K)$ that guarantee $Q_{next} = \overline{Q}$ for any initial state $Q$ is

A.
0
B.
1
C.
2
D.
4

Correct Answer:

Step-by-Step Solution

Insight: This is an observation question about the JK flip-flop characteristic equation and the specific condition for toggling.

Exam route: Set $Q_{next} = \overline{Q}$ in the equation and solve for $J$ and $K$ that hold for both $Q = 0$ and $Q = 1$ .

Learning route:

Step 1: The characteristic equation is $Q_{next} = J \overline{Q} + \overline{K} Q$ .

Step 2: We require $Q_{next} = \overline{Q}$ for any initial state $Q$ .

Step 3: If $Q = 0$ , then $\overline{Q} = 1$ . The equation becomes $1 = J (1) + \overline{K} (0) \Rightarrow J = 1$ .

Step 4: If $Q = 1$ , then $\overline{Q} = 0$ . The equation becomes $0 = J (0) + \overline{K} (1) \Rightarrow \overline{K} = 0 \Rightarrow K = 1$ .

Step 5: The only input pair that satisfies both conditions simultaneously is $J = 1, K = 1$ .

Step 6: Thus, there is exactly 1 such input pair.

Answer: 1

Question 3 · Digital Logic MCQ

Consider a 3-bit ripple counter with flip-flop propagation delay of 20 ns and a strobe delay of 20 ns. Which of the following statements regarding its maximum operating frequency is true?

A.
The maximum frequency is 16.67 MHz because the strobe delay does not affect the critical path.
B.
The maximum frequency is 12.5 MHz because the total critical path delay is 80 ns.
C.
The maximum frequency is 10.0 MHz because the total critical path delay is 100 ns.
D.
The maximum frequency is 25.0 MHz because only one flip-flop delay matters.

Correct Answer:

Step-by-Step Solution

Insight: This is a bounding question testing the complete maximum frequency formula for a ripple counter, including the strobe delay.

Exam route: Calculate total delay as $n \times t_{p d} + t_{s t r o b e}$ , then take the reciprocal to find $f_{ma x}$ .

Learning route:

Step 1: Identify the parameters: $n = 3$ , $t_{p d} = 20 ns$ , $t_{s t r o b e} = 20 ns$ .

Step 2: Calculate the minimum clock period required for stable operation:

$T_{c l k (min)} = n \cdot t_{p d} + t_{s t r o b e}$

$T_{c l k (min)} = 3 \times 20 ns + 20 ns = 60 ns + 20 ns = 80 ns$

Step 3: Calculate the maximum operating frequency:

$f_{ma x} = \frac{1}{T _{c l k (min)}} = \frac{1}{80 \times 1 0 ^{- 9} s} = 12.5 \times 1 0^{6} Hz = 12.5 MHz$

Answer: The maximum frequency is 12.5 MHz because the total critical path delay is 80 ns.

Question 4 · Digital Logic MCQ

A sequential circuit has 2 D flip-flops and 2 external inputs. The complete state table lists every combination of current state and input values. How many rows does this state table contain?

A.
4
B.
8
C.
16
D.
32

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct application of the state table sizing rule from the sequential circuit fundamentals.

Step 1: Determine the number of distinct current states. With $n = 2$ flip-flops, the number of states is $2^{n} = 2^{2} = 4$ .

Step 2: Determine the number of input combinations. With $m = 2$ external inputs, the number of input combinations is $2^{m} = 2^{2} = 4$ .

Step 3: The state table must cover every (current state, input) pair. The total number of rows is the product:

$Rows = 2^{n} \times 2^{m} = 4 \times 4 = 16$

Answer: C

Question 5 · Digital Logic MCQ

A sequential circuit must be capable of representing at least 4 distinct states. What is the minimum number of flip-flops required?

A.
2
B.
3
C.
4
D.
8

Correct Answer:

Step-by-Step Solution

Key idea: This is a direct application of the relationship between flip-flop count and state capacity.

Step 1: With $n$ flip-flops, a sequential circuit can represent up to $2^{n}$ distinct states.

Step 2: We need at least 4 states. Find the smallest $n$ such that $2^{n} \geq 4$ .

Step 3: Check values:

$n = 1$ : $2^{1} = 2 < 4$ (not enough)
$n = 2$ : $2^{2} = 4 \geq 4$ (sufficient)

The minimum number of flip-flops is 2.

Answer: A

Question 6 · Digital Logic MCQ

A sequential circuit has 3 state variables and 2 external inputs. The output function of a Mealy machine depends on $n + m$ variables, while a Moore machine depends on $n$ variables. The difference in the number of variables the output function depends on between a Mealy and a Moore implementation of this circuit is

A.
-2
B.
0
C.
2
D.
5

Correct Answer:

Step-by-Step Solution

Insight: This is a casework question comparing the variable dependency of Mealy and Moore machine output functions.

Exam route: For Mealy, dependency is $n + m$ . For Moore, dependency is $n$ . Substitute $n = 3, m = 2$ and find the difference.

Learning route:

Step 1: Identify the number of state variables $n = 3$ and external inputs $m = 2$ .

Step 2: For a Mealy machine, the output function depends on current state and inputs: $n + m = 3 + 2 = 5$ variables.

Step 3: For a Moore machine, the output function depends only on the current state: $n = 3$ variables.

Step 4: Calculate the difference: $5 - 3 = 2$ .

Answer: 2

Question 7 · Digital Logic MCQ

Consider a sequential circuit with three flip-flops: $Q_{1}$ and $Q_{2}$ are T flip-flops, and $Q_{3}$ is a D flip-flop. The connections are $T_{1} = Q_{2} \cdot Q_{3}$ , $T_{2} = Q_{1}$ , and $D_{3} = Q_{1} \oplus Q_{2}$ . The circuit is initialized to $Q_{1} Q_{2} Q_{3} = 011$ . Which of the following statements about the state sequence is true?

A.
The circuit visits exactly 4 distinct states before repeating.
B.
The state 000 is an absorbing state, and the circuit never returns to 011.
C.
The circuit oscillates indefinitely between 011 and 111.
D.
The state 111 transitions directly back to 011 in one clock cycle.

Correct Answer:

Step-by-Step Solution

Insight: This is a state-tracing question. We must compute the next state for each flip-flop simultaneously using the given excitation equations.

Exam route: Start at 011. Compute $T_{1}, T_{2}, D_{3}$ . Apply $Q_{next} = T \oplus Q$ for T-FF and $Q_{next} = D$ for D-FF. Repeat until a pattern or absorbing state is found.

Learning route:

Step 1: Initial state is $Q_{1} Q_{2} Q_{3} = 011$ .

Step 2: Clock 1:

$T_{1} = Q_{2} \cdot Q_{3} = 1 \cdot 1 = 1$ . $Q_{1, next} = 1 \oplus 0 = 1$ .

$T_{2} = Q_{1} = 0$ . $Q_{2, next} = 0 \oplus 1 = 1$ .

$D_{3} = Q_{1} \oplus Q_{2} = 0 \oplus 1 = 1$ . $Q_{3, next} = 1$ .

New state: 111.

Step 3: Clock 2 (from 111):

$T_{1} = 1 \cdot 1 = 1$ . $Q_{1, next} = 1 \oplus 1 = 0$ .

$T_{2} = 1$ . $Q_{2, next} = 1 \oplus 1 = 0$ .

$D_{3} = 1 \oplus 1 = 0$ . $Q_{3, next} = 0$ .

New state: 000.

Step 4: Clock 3 (from 000):

$T_{1} = 0 \cdot 0 = 0$ . $Q_{1, next} = 0 \oplus 0 = 0$ .

$T_{2} = 0$ . $Q_{2, next} = 0 \oplus 0 = 0$ .

$D_{3} = 0 \oplus 0 = 0$ . $Q_{3, next} = 0$ .

New state: 000.

The state 000 is absorbing. The distinct states visited are 011, 111, and 000. The circuit never returns to 011.

Answer: The state 000 is an absorbing state, and the circuit never returns to 011.

Question 8 · Digital Logic MCQ

In an 8-bit synchronous counter, the propagation delay of each flip-flop is 15 ns and the maximum delay of the combinational logic is 25 ns. The maximum total propagation delay for any state transition is

A.
40 ns
B.
120 ns
C.
145 ns
D.
200 ns

Correct Answer:

Step-by-Step Solution

Insight: This is an observation question testing the fundamental speed advantage of synchronous counters.

Exam route: Recall that in a synchronous counter, total delay is independent of the number of bits. It is simply $t_{p d} (FF) + t_{p d} (logic)$ .

Learning route:

Step 1: Identify the counter type: synchronous.

Step 2: Recall the delay formula for synchronous counters: all flip-flops trigger simultaneously, so the delay does not accumulate across stages.

Step 3: The total delay is bounded by the delay of one flip-flop plus the delay of the combinational logic determining the next state.

Step 4: Calculate: $15 ns + 25 ns = 40 ns$ .

Answer: 40 ns

Question 9 · Digital Logic MCQ

Consider the following assertion and reason regarding a sequential circuit:

Assertion (A): In a ripple counter built with negative-edge-triggered flip-flops, connecting the clock input of each stage to the $\overline{Q}$ output of the previous stage results in a DOWN counter.

Reason (R): When the current state bit transitions from 0 to 1, its $\overline{Q}$ output transitions from 1 to 0, providing the required negative clock edge to trigger the next stage.

A.
Both A and R are true, and R is the correct explanation of A.
B.
Both A and R are true, but R is not the correct explanation of A.
C.
A is true but R is false.
D.
A is false but R is true.

Correct Answer:

Step-by-Step Solution

Insight: This is a construction question testing the precise wiring rules for ripple counter direction based on clock trigger edges.

Exam route: Verify the down-count sequence behavior. In a down counter, the next bit toggles when the current bit goes $0 \to 1$ . Check if $\overline{Q}$ provides a negative edge during this transition.

Learning route:

Step 1: Analyze the down-count sequence. For a bit to decrement the overall count, the next higher bit must toggle when the current bit transitions from 0 to 1.

Step 2: Evaluate the signal at $\overline{Q}$ during this $0 \to 1$ transition of $Q$ . When $Q$ goes from 0 to 1, $\overline{Q}$ goes from 1 to 0.

Step 3: A $1 \to 0$ transition is a negative edge.

Step 4: Since the flip-flops are negative-edge-triggered, connecting the next stage's clock to $\overline{Q}$ will correctly trigger the next stage exactly when needed for a down-count.

Step 5: Both A and R are true, and R perfectly explains the mechanism described in A.

Answer: Both A and R are true, and R is the correct explanation of A.

Question 10 · Digital Logic MCQ

For a D flip-flop, the excitation input $D$ is required to be equal to the next state $Q^{+}$ . If the current state is $Q = 1$ and the desired next state is $Q^{+} = 0$ , what is the value of the excitation input $D$ ?

A.
0
B.
1
C.
X (Don't Care)
D.
Undefined

Correct Answer:

Step-by-Step Solution

Key idea: The D flip-flop simply passes the input $D$ to the output $Q$ on the clock edge. Thus, $D$ must exactly equal the desired next state $Q^{+}$ .

Step 1: Identify the desired next state, which is given as $Q^{+} = 0$ .

Step 2: Apply the rule for a D flip-flop: $D = Q^{+}$ .

Step 3: Substitute the value: $D = 0$ .

Conclusion: The value of the excitation input $D$ is 0.

flip flops counters and finite state machines short notes

Topic Summary: Sequential Circuit Analysis Checklist

Final Checklist

Before Starting:

Analysis Steps:

Tracing:

Verification:

Characteristic Equations (Memorize)

If You See...

Topic Summary: Counter Analysis Checklist

Final Checklist

1. Identify the Architecture

2. Ripple Counter Direction (Negative-Edge FFs)

3. Frequency & Delay

4. Synchronous Analysis Method

Final Revision Checklist

Final Revision Checklist

Try a question

Login to view the complete short notes

Personalised first. High quality throughout.

Built around you, not around a syllabus PDF

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Questions calibrated to the real exam

Notes written for recall, not for volume

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Unlock the whole course

Flip-Flops, Counters and Finite State Machines Short Notes for GATE CS

Topic Summary: Sequential Circuit Analysis Checklist

Final Checklist

Before Starting:

Analysis Steps:

Tracing:

Verification:

Characteristic Equations (Memorize)

If You See...

Topic Summary: Counter Analysis Checklist

Final Checklist

1. Identify the Architecture

2. Ripple Counter Direction (Negative-Edge FFs)

3. Frequency & Delay

4. Synchronous Analysis Method

Final Revision Checklist

Final Revision Checklist

Final Revision Checklist

Final Revision Checklist

Flip-Flops, Counters and Finite State Machines: Solved Questions with Step-by-Step Explanations (10 Problems)

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

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