Memory Management, Paging and Virtual Memory PYQs for GATE CS
Solve 14+ Memory Management, Paging and Virtual Memory previous year questions for GATE CS with answers and detailed solutions. Free sample questions below.
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Question 1
2026 Slot Set2 PYQ
A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is ___________. (answer in integer)
Note:1K=210, 1M=220, 1G=230
Question 2
2026 Slot Set2 PYQ
Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are 8 holes in the memory of sizes 20 KB, 4 KB, 25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are adjacent. Two processes P1 of size 16 KB and P2 of size 9 KB arrive in that order, and they are allocated memory using the best-fit technique. After allocating space to P1 and P2, the number of holes of size less than 8 KB is ____________. (answer in integer)
Note:1K=210
Question 3
2025 Slot Set2 PYQ
A computer system supports a logical address space of 232 bytes. It uses two-level hierarchical paging with a page size of 4096 bytes. A logical address is divided into a b-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight bytes. All the pages in the system have the same size.
The value of b is ___________ . (Answer in integer)
Question 4
2025 Slot Set2 PYQ
Consider a demand paging system with three frames, and the following page reference string: 1 2 3 4 5 4 1 6 4 5 1 3 2. The contents of the frames are as follows initially and after each reference (from left to right):
The *-marked references cause page replacements.
Which one or more of the following could be the page replacement policy/policies in use?
Question 5
2025 Slot Set1 PYQ
Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
Question 6
2025 Slot Set1 PYQ
In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows:
The OS correctly predicts only up to next 4 page references (including the current page) at the time of allocating a frame to a page.
A process accesses the pages in the following order of page numbers:
1,3,2,4,2,3,1,2,4,3,1,4. If the system has three memory frames that are initially empty, the number of page faults that will occur during execution of the process is ________. (Answer in integer)
Question 7
2024 Slot Set2 PYQ
Consider a 32-bit system with 4 KB page size and page table entries of size 4 bytes each. Assume 1 KB = 210 bytes. The OS uses a 2-level page table for memory management, with the page table containing an outer page directory and an inner page table. The OS allocates a page for the outer page directory upon process creation. The OS uses demand paging when allocating memory for the inner page table, i.e., a page of the inner page table is allocated only if it contains at least one valid page table entry.
An active process in this system accesses 2000 unique pages during its execution, and none of the pages are swapped out to disk. After it completes the page accesses, let X denote the minimum and Y denote the maximum number of pages across the two levels of the page table of the process.
The value of X+Y is __________
Question 8
2024 Slot Set2 PYQ
Which of the following tasks is/are the responsibility/responsibilities of the memory management unit (MMU) in a system with paging-based memory management?
Question 9
2024 Slot Set1 PYQ
Consider a memory management system that uses a page size of 2 KB. Assume that both the physical and virtual addresses start from 0. Assume that the pages 0, 1, 2, and 3 are stored in the page frames 1, 3, 2, and 0, respectively. The physical address <i>(in decimal format)</i> corresponding to the virtual address 2500 <i>(in decimal format)</i> is _________
Question 10
2023 PYQ
Consider the following two-dimensional array D in the C programming language, which is stored in row-major order:
int D[128][128];
Demand paging is used for allocating memory and each physical page frame holds 512 elements of the array D. The Least Recently Used (LRU) page-replacement policy is used by the operating system. A total of 30 physical page frames are allocated to a process which executes the following code snippet:
for (int i = 0; i < 128; i++) for (int j = 0; j < 128; j++) D[j][i] *= 10;
The number of page faults generated during the execution of this code snippet is __________.
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Memory Management, Paging and Virtual Memory PYQs for GATE CS
Solve 14+ Memory Management, Paging and Virtual Memory previous year questions for GATE CS with answers and detailed solutions. Free sample questions below.
Paging and Address Translation Scope
Paging and Address Translation Scope
Paging divides memory into fixed-size blocks called pages in virtual memory and frames in physical memory. For example, if a system has a 32 KB virtual space and a 4 KB page size, it creates exactly 8 pages. The symbol V represents the virtual address space size, P represents the page size, and the number of pages is V/P.
Explain this more simply
Think of a book. The book is the virtual address space. Each page of the book is a fixed size. The bookshelf is physical memory, divided into slots of the exact same size. The page table is the index at the back of the book, telling you which slot holds which page.
Go one level deeper
The page size P is always a power of two. This ensures the page offset can be extracted using a simple bitwise AND operation, avoiding expensive division hardware in the Memory Management Unit (MMU), which is the hardware component responsible for address translation.
Virtual versus Physical Address Spaces
A virtual address is generated by the CPU and represents a location in the process's logical address space. A physical address is the actual location in the main memory hardware. For instance, virtual page 3 might map to physical frame 7. The symbol v denotes a virtual address, and p denotes a physical address. The mapping is many-to-one in terms of potential locations, but one-to-one for active pages.
Explain this more simply
Imagine a hotel. The room numbers (virtual addresses) are sequential and make sense to the guest. The actual physical location of the room in the building (physical address) might be scattered across different wings. The front desk (page table) knows exactly which physical room corresponds to which room number.
Go one level deeper
The virtual address space can be larger than the physical address space. This is the foundation of virtual memory, allowing processes to be larger than available RAM by keeping inactive pages on secondary storage, though secondary storage mechanics are handled by page fault routines outside this specific scope.
Memory Management, Paging and Virtual Memory: Solved Questions with Step-by-Step Explanations (10 Problems)
Question 1 · Operating System · 2026_Set2NAT
A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is ___________. (answer in integer)
Note:1K=210, 1M=220, 1G=230
Question 2 · Operating System · 2026_Set2NAT
Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are 8 holes in the memory of sizes 20 KB, 4 KB, 25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are adjacent. Two processes P1 of size 16 KB and P2 of size 9 KB arrive in that order, and they are allocated memory using the best-fit technique. After allocating space to P1 and P2, the number of holes of size less than 8 KB is ____________. (answer in integer)
Note:1K=210
Question 3 · Operating System · 2025_Set2NAT
A computer system supports a logical address space of 232 bytes. It uses two-level hierarchical paging with a page size of 4096 bytes. A logical address is divided into a b-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight bytes. All the pages in the system have the same size.
The value of b is ___________ . (Answer in integer)
Question 4 · Operating System · 2025_Set2MSQ
Consider a demand paging system with three frames, and the following page reference string: 1 2 3 4 5 4 1 6 4 5 1 3 2. The contents of the frames are as follows initially and after each reference (from left to right):
The *-marked references cause page replacements.
Which one or more of the following could be the page replacement policy/policies in use?
A.
Least Recently Used page replacement policy
B.
Least Frequently Used page replacement policy
C.
Most Frequently Used page replacement policy
D.
Optimal page replacement policy
Question 5 · Operating System · 2025_Set1MCQ
Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
A.
221
B.
220
C.
222
D.
224
Question 6 · Operating System · 2025_Set1NAT
In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows:
The OS correctly predicts only up to next 4 page references (including the current page) at the time of allocating a frame to a page.
A process accesses the pages in the following order of page numbers:
1,3,2,4,2,3,1,2,4,3,1,4. If the system has three memory frames that are initially empty, the number of page faults that will occur during execution of the process is ________. (Answer in integer)
Question 7 · Operating System · 2024_Set2NAT
Consider a 32-bit system with 4 KB page size and page table entries of size 4 bytes each. Assume 1 KB = 210 bytes. The OS uses a 2-level page table for memory management, with the page table containing an outer page directory and an inner page table. The OS allocates a page for the outer page directory upon process creation. The OS uses demand paging when allocating memory for the inner page table, i.e., a page of the inner page table is allocated only if it contains at least one valid page table entry.
An active process in this system accesses 2000 unique pages during its execution, and none of the pages are swapped out to disk. After it completes the page accesses, let X denote the minimum and Y denote the maximum number of pages across the two levels of the page table of the process.
The value of X+Y is __________
Question 8 · Operating System · 2024_Set2MSQ
Which of the following tasks is/are the responsibility/responsibilities of the memory management unit (MMU) in a system with paging-based memory management?
A.
Allocate a new page table for a newly created process
B.
Translate a virtual address to a physical address using the page table
C.
Raise a trap when a virtual address is not found in the page table
D.
Raise a trap when a process tries to write to a page marked with read-only permission in the page table
Question 9 · Operating System · 2024_Set1NAT
Consider a memory management system that uses a page size of 2 KB. Assume that both the physical and virtual addresses start from 0. Assume that the pages 0, 1, 2, and 3 are stored in the page frames 1, 3, 2, and 0, respectively. The physical address <i>(in decimal format)</i> corresponding to the virtual address 2500 <i>(in decimal format)</i> is _________
Question 10 · Operating System · 2023NAT
Consider the following two-dimensional array D in the C programming language, which is stored in row-major order:
int D[128][128];
Demand paging is used for allocating memory and each physical page frame holds 512 elements of the array D. The Least Recently Used (LRU) page-replacement policy is used by the operating system. A total of 30 physical page frames are allocated to a process which executes the following code snippet:
for (int i = 0; i < 128; i++) for (int j = 0; j < 128; j++) D[j][i] *= 10;
The number of page faults generated during the execution of this code snippet is __________.