Digital Logic PYQs for GATE CS

GATE CS Digital Logic: 1 units and 4 chapters, weightage from 33 previous year questions across 10 papers, a study order by exam weight and 537 practice questions.

About Digital Logic Previous Year Questions (PYQs)

33 previous year questions from Digital Logic in GATE CS, grouped by chapter with the exam year, answer key and step-by-step solution for each.

GATE CS Digital Logic Unit-wise Weightage from Past Papers

We counted every GATE CS Digital Logic previous year question in our bank (33 questions from 10 papers) and grouped them by unit.

Unit	Chapters	PYQs	Share of section	Avg per paper
Digital Logic	4	33	100%	3.3

Suggested Digital Logic Study Order for GATE CS

Digital Logic: 100% of past Digital Logic questions, about 3.3 per paper.

Start where the marks are. Units at the top of this list have appeared most often in past GATE CS papers.

Units in GATE CS Digital Logic

Digital Logic Previous Year Questions (PYQs) (4 chapters)

All Digital Logic chapters

One Solved Question from Each Digital Logic Chapter

Question 1 · Number Systems, Binary Arithmetic and Data Representation · 2024_Set2 MSQ

Which of the following is/are EQUAL to 224 in radix-5 (i.e., base-5) notation?

A.
64 in radix-10
B.
100 in radix-8
C.
50 in radix-16
D.
121 in radix-7

Correct Answer:

["A","B","D"]

Step-by-Step Solution

Insight: Convert the given Base 5 number to Base 10, then convert each option to Base 10 to check for equality.

Exam route:

$(224)_{5} = 2 (25) + 2 (5) + 4 (1) = 50 + 10 + 4 = 6 4_{10}$ .
Check options in Base 10:

A) $6 4_{10} = 64$ . (Match)

B) $(100)_{8} = 1 (64) = 64$ . (Match)

C) $(50)_{16} = 5 (16) = 80$ . (No match)

D) $(121)_{7} = 1 (49) + 2 (7) + 1 (1) = 49 + 14 + 1 = 64$ . (Match)

Learning route:

This is a multiple-select question testing base equivalence. The most efficient strategy is to anchor everything to Base 10.

Step 1: Convert the target number $(224)_{5}$ to Base 10.

$2 \times 5^{2} + 2 \times 5^{1} + 4 \times 5^{0} = 2 (25) + 10 + 4 = 6 4_{10}$ .

Step 2: Evaluate each option in Base 10.

Option A: $6 4_{10}$ is already in Base 10. Value is 64. (Equal)

Option B: $(100)_{8} = 1 \times 8^{2} = 6 4_{10}$ . (Equal)

Option C: $(50)_{16} = 5 \times 1 6^{1} + 0 = 8 0_{10}$ . (Not equal)

Option D: $(121)_{7} = 1 \times 7^{2} + 2 \times 7^{1} + 1 \times 7^{0} = 49 + 14 + 1 = 6 4_{10}$ . (Equal)

The correct options are A, B, and D.

Question 2 · Boolean Algebra, Canonical Forms and Logic Minimization · 2026_Set2 MCQ

Which one of the following options is not a property of Boolean Algebra?

Note:

+

is OR operation,

.

is AND operation, and

^{'}

is NOT operation

A.
$a + b = b + a$
B.
$a . a^{'} = 1$
C.
$a + a^{'} = 1$
D.
$a . b = b . a$

Correct Answer:

Step-by-Step Solution

Insight: Recall the fundamental axioms of Boolean algebra, specifically the complement laws.

Exam route: $a \cdot a^{'} = 0$ , not $1$ . The other options are standard commutative and complement laws.

Learning route:

Let's evaluate each option against the standard axioms of Boolean algebra:

Option A: $a + b = b + a$ . This is the Commutative Law for OR. (Property)

Option B: $a \cdot a^{'} = 1$ . The Complement Law states that a variable ANDed with its complement is always 0, not 1. ( $a \cdot a^{'} = 0$ ). (NOT a property)

Option C: $a + a^{'} = 1$ . This is the correct Complement Law for OR. (Property)

Option D: $a \cdot b = b \cdot a$ . This is the Commutative Law for AND. (Property)

Therefore, Option B is the only one that is not a valid property.

Question 3 · Combinational Logic Circuits and Data Selectors · 2026_Set2 NAT

Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent active high 2:4 decoder and 4-to-1 multiplexer, respectively. Out of 16 possible input combinations, the number of combinations that produce Y=1 is ____________. (answer in integer)

Note: One input combination is an instance of [A B S1 S0].

Correct Answer:

4.00

Step-by-Step Solution

Insight: The decoder generates mutually exclusive minterms of its inputs, and the MUX simply selects one of these minterms based on its own select lines.

Exam route: Write the MUX output equation $Y = \sum S_{i} I_{i}$ . Substitute the decoder outputs $D_{i}$ for $I_{i}$ . Since $D_{i}$ are minterms of A and B, each product term in the sum represents a unique, non-overlapping combination of all 4 variables [A, B, S1, S0]. Count the valid terms.

Learning route:

The 2-to-4 decoder Q has inputs A and B. Its active-high outputs are the minterms of A and B:

$D_{0} = \overline{A} \overline{B}$
$D_{1} = \overline{A} B$
$D_{2} = A \overline{B}$
$D_{3} = A B$

These outputs are connected directly to the data inputs of the 4-to-1 MUX M: $I_{0} = D_{0}, I_{1} = D_{1}, I_{2} = D_{2}, I_{3} = D_{3}$ .
The MUX has select lines $S_{1}$ and $S_{0}$ . Its output equation is:

$Y = \overline{S_{1}} \overline{S_{0}} I_{0} + \overline{S_{1}} S_{0} I_{1} + S_{1} \overline{S_{0}} I_{2} + S_{1} S_{0} I_{3}$

Substitute the decoder outputs into the MUX equation:

$Y = \overline{S_{1}} \overline{S_{0}} \overline{A} \overline{B} + \overline{S_{1}} S_{0} \overline{A} B + S_{1} \overline{S_{0}} A \overline{B} + S_{1} S_{0} A B$

We need to find the number of input combinations [A, B, S1, S0] that make $Y = 1$ .
Analyze each term:

Term 1 is 1 only when $S_{1} = 0, S_{0} = 0, A = 0, B = 0$ . (1 combination: 0000)
Term 2 is 1 only when $S_{1} = 0, S_{0} = 1, A = 0, B = 1$ . (1 combination: 0101)
Term 3 is 1 only when $S_{1} = 1, S_{0} = 0, A = 1, B = 0$ . (1 combination: 1010)
Term 4 is 1 only when $S_{1} = 1, S_{0} = 1, A = 1, B = 1$ . (1 combination: 1111)

Since these four product terms are mutually exclusive (they represent distinct minterms of the 4 variables), there are exactly 4 combinations that produce $Y = 1$ .

Question 4 · Flip-Flops, Counters and Finite State Machines · 2026_Set1 MCQ

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input

P

is 0, and the saturating down count when

P

is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.

Input	Current State		Next State
$P$	$Q_{1}$	$Q_{0}$	$Q_{1}^{+}$	$Q_{0}^{+}$
0	0	0	0	1
0	0	1	1	0
0	1	0	1	1
0	1	1	1	1
1	0	0	0	0
1	0	1	0	0
1	1	0	0	1
1	1	1	1	0

Which one of the following options corresponds to the expressions for the inputs of the D flip-flops,

D_{1}

and

D_{0}

A.
$D_{1} = P Q_{1} + \overline{P} Q_{0} + Q_{1} Q_{0} D_{0} = P Q_{0} + \overline{P} Q_{1} + Q_{1} \overline{Q_{0}}$
B.
$D_{1} = \overline{P} Q_{1} + \overline{P} Q_{0} + Q_{1} Q_{0} D_{0} = \overline{P} \overline{Q_{0}} + \overline{P} Q_{1} + Q_{1} \overline{Q_{0}}$
C.
$D_{1} = \overline{P} \overline{Q_{1}} + \overline{P} Q_{0} + Q_{1} Q_{0} D_{0} = \overline{P} Q_{0} + \overline{P} Q_{1} + Q_{1} \overline{Q_{0}}$
D.
$D_{1} = P \overline{Q_{1}} + \overline{P} Q_{0} + Q_{1} Q_{0} D_{0} = P \overline{Q_{0}} + \overline{P} Q_{1} + Q_{1} \overline{Q_{0}}$

Correct Answer:

Step-by-Step Solution

Insight: For D flip-flops, the excitation input is exactly the next state ( $D = Q^{+}$ ). We just need to map the given Next State table to K-maps for $D_{1}$ and $D_{0}$ and minimize them.

Exam route: Build K-maps for $D_{1}$ and $D_{0}$ with variables $P, Q_{1}, Q_{0}$ . Fill in the 1s from the $Q_{1}^{+}$ and $Q_{0}^{+}$ columns. Group the 1s to get the SOP expressions. Match with the options.

Learning route:

Step 1: Understand the D flip-flop excitation. $D_{1} = Q_{1}^{+}$ and $D_{0} = Q_{0}^{+}$ .

Step 2: Construct the K-map for $D_{1}$ .

The minterms where $Q_{1}^{+} = 1$ are:

$P = 0, Q_{1} = 0, Q_{0} = 1$ (m1)

$P = 0, Q_{1} = 1, Q_{0} = 0$ (m2)

$P = 0, Q_{1} = 1, Q_{0} = 1$ (m3)

$P = 1, Q_{1} = 1, Q_{0} = 1$ (m7)

Grouping these on a 3-variable K-map:

m3 and m7 form a pair $\to Q_{1} Q_{0}$
m1 and m3 form a pair $\to \overline{P} Q_{0}$
m2 and m3 form a pair $\to \overline{P} Q_{1}$

Thus, $D_{1} = Q_{1} Q_{0} + \overline{P} Q_{0} + \overline{P} Q_{1}$ .

Step 3: Construct the K-map for $D_{0}$ .

The minterms where $Q_{0}^{+} = 1$ are:

$P = 0, Q_{1} = 0, Q_{0} = 0$ (m0)

$P = 0, Q_{1} = 1, Q_{0} = 0$ (m2)

$P = 0, Q_{1} = 1, Q_{0} = 1$ (m3)

$P = 1, Q_{1} = 1, Q_{0} = 0$ (m6)

Grouping these:

m2 and m6 form a pair $\to Q_{1} \overline{Q_{0}}$
m0 and m2 form a pair $\to \overline{P} \overline{Q_{0}}$
m2 and m3 form a pair $\to \overline{P} Q_{1}$

Thus, $D_{0} = Q_{1} \overline{Q_{0}} + \overline{P} \overline{Q_{0}} + \overline{P} Q_{1}$ .

Step 4: Match with options. Option B matches both derived expressions perfectly.

Verification: Plug in $P = 0, Q_{1} = 1, Q_{0} = 0$ into Option B. $D_{1} = (1) (0) + (1) (0) + (1) (1) = 1$ . $D_{0} = (1) (1) + (1) (1) + (1) (1) = 1$ . This matches the table's Next State of 11.

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Digital Logic PYQs for GATE CS

About Digital Logic Previous Year Questions (PYQs)

GATE CS Digital Logic Unit-wise Weightage from Past Papers

Suggested Digital Logic Study Order for GATE CS

Units in GATE CS Digital Logic

All Digital Logic chapters

One Solved Question from Each Digital Logic Chapter

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution

Step-by-Step Solution